Commit 54eff226 authored by Michał Mirosław's avatar Michał Mirosław Committed by Thierry Reding

clk: tegra: Fix cclk_lp divisor register

According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: b08e8c0e ("clk: tegra: add clock support for Tegra30")
Signed-off-by: default avatarMichał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-By: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d80a32fe
...@@ -965,7 +965,7 @@ static void __init tegra30_super_clk_init(void) ...@@ -965,7 +965,7 @@ static void __init tegra30_super_clk_init(void)
* U71 divider of cclk_lp. * U71 divider of cclk_lp.
*/ */
clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
clk_base + SUPER_CCLKG_DIVIDER, 0, clk_base + SUPER_CCLKLP_DIVIDER, 0,
TEGRA_DIVIDER_INT, 16, 8, 1, NULL); TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
......
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