Commit 55bfc376 authored by Qin Jian's avatar Qin Jian Committed by Arnd Bergmann

dt-bindings: reset: Add bindings for SP7021 reset driver

Add documentation to describe Sunplus SP7021 reset driver bindings.
Signed-off-by: default avatarQin Jian <qinjian@cqplus1.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 8bbb1dd5
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Sunplus SoC Reset Controller
maintainers:
- Qin Jian <qinjian@cqplus1.com>
properties:
compatible:
const: sunplus,sp7021-reset
reg:
maxItems: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- "#reset-cells"
additionalProperties: false
examples:
- |
rstc: reset@9c000054 {
compatible = "sunplus,sp7021-reset";
reg = <0x9c000054 0x28>;
#reset-cells = <1>;
};
...
......@@ -2831,6 +2831,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers)
S: Maintained
W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml
F: include/dt-bindings/reset/sunplus,sp7021-reset.h
ARM/Synaptics SoC support
M: Jisheng Zhang <jszhang@kernel.org>
......
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) Sunplus Technology Co., Ltd.
* All rights reserved.
*/
#ifndef _DT_BINDINGS_RST_SUNPLUS_SP7021_H
#define _DT_BINDINGS_RST_SUNPLUS_SP7021_H
#define RST_SYSTEM 0
#define RST_RTC 1
#define RST_IOCTL 2
#define RST_IOP 3
#define RST_OTPRX 4
#define RST_NOC 5
#define RST_BR 6
#define RST_RBUS_L00 7
#define RST_SPIFL 8
#define RST_SDCTRL0 9
#define RST_PERI0 10
#define RST_A926 11
#define RST_UMCTL2 12
#define RST_PERI1 13
#define RST_DDR_PHY0 14
#define RST_ACHIP 15
#define RST_STC0 16
#define RST_STC_AV0 17
#define RST_STC_AV1 18
#define RST_STC_AV2 19
#define RST_UA0 20
#define RST_UA1 21
#define RST_UA2 22
#define RST_UA3 23
#define RST_UA4 24
#define RST_HWUA 25
#define RST_DDC0 26
#define RST_UADMA 27
#define RST_CBDMA0 28
#define RST_CBDMA1 29
#define RST_SPI_COMBO_0 30
#define RST_SPI_COMBO_1 31
#define RST_SPI_COMBO_2 32
#define RST_SPI_COMBO_3 33
#define RST_AUD 34
#define RST_USBC0 35
#define RST_USBC1 36
#define RST_UPHY0 37
#define RST_UPHY1 38
#define RST_I2CM0 39
#define RST_I2CM1 40
#define RST_I2CM2 41
#define RST_I2CM3 42
#define RST_PMC 43
#define RST_CARD_CTL0 44
#define RST_CARD_CTL1 45
#define RST_CARD_CTL4 46
#define RST_BCH 47
#define RST_DDFCH 48
#define RST_CSIIW0 49
#define RST_CSIIW1 50
#define RST_MIPICSI0 51
#define RST_MIPICSI1 52
#define RST_HDMI_TX 53
#define RST_VPOST 54
#define RST_TGEN 55
#define RST_DMIX 56
#define RST_TCON 57
#define RST_INTERRUPT 58
#define RST_RGST 59
#define RST_GPIO 60
#define RST_RBUS_TOP 61
#define RST_MAILBOX 62
#define RST_SPIND 63
#define RST_I2C2CBUS 64
#define RST_SEC 65
#define RST_DVE 66
#define RST_GPOST0 67
#define RST_OSD0 68
#define RST_DISP_PWM 69
#define RST_UADBG 70
#define RST_DUMMY_MASTER 71
#define RST_FIO_CTL 72
#define RST_FPGA 73
#define RST_L2SW 74
#define RST_ICM 75
#define RST_AXI_GLOBAL 76
#endif
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