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Commit 56116dc7 authored by Alex Hung's avatar Alex Hung Committed by Alex Deucher
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Revert "drm/amd/display: Enable SYMCLK gating in DCCG" 

This reverts commit c49e44ed.

This causes regression on DP link layer test.
Reported-by: default avatarMark Broadworth <Mark.Broadworth@amd.com>
Acked-by: default avatarRodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 85cf43c5
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Showing with 48 additions and 115 deletions
drivers/gpu/drm/amd/display/dc/dc.h
View file @ 56116dc7
......@@ -728,7 +728,6 @@ enum pg_hw_pipe_resources {
PG_DPSTREAM,
PG_HDMISTREAM,
PG_PHYSYMCLK,
PG_SYMCLK,
PG_HW_PIPE_RESOURCES_NUM_ELEMENT
};
......
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
View file @ 56116dc7
......@@ -655,61 +655,9 @@ static void dccg35_disable_symclk32_se(
}
}
static void dccg35_set_symclk_root_clock_gating(struct dccg *dccg, uint32_t stream_enc_inst,
uint32_t link_enc_inst, bool enable)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
switch (stream_enc_inst) {
case 0:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, enable ? 1 : 0);
break;
case 1:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, enable ? 1 : 0);
break;
case 2:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, enable ? 1 : 0);
break;
case 3:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, enable ? 1 : 0);
break;
case 4:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, enable ? 1 : 0);
break;
}
switch (link_enc_inst) {
case 0:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, enable ? 1 : 0);
break;
case 1:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, enable ? 1 : 0);
break;
case 2:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, enable ? 1 : 0);
break;
case 3:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, enable ? 1 : 0);
break;
case 4:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, enable ? 1 : 0);
break;
}
}
void dccg35_init(struct dccg *dccg)
{
int otg_inst, phy_inst;
int otg_inst;
/* Set HPO stream encoder to use refclk to avoid case where PHY is
* disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which
* will cause DCN to hang.
......@@ -723,9 +671,10 @@ void dccg35_init(struct dccg *dccg)
dccg31_set_symclk32_le_root_clock_gating(dccg, otg_inst, false);
}
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
for (phy_inst = 0; phy_inst < 5; phy_inst++)
dccg35_set_symclk_root_clock_gating(dccg, phy_inst, phy_inst, false);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
// for (otg_inst = 0; otg_inst < 4; otg_inst++)
// dccg35_disable_symclk_se(dccg, otg_inst, otg_inst);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
for (otg_inst = 0; otg_inst < 4; otg_inst++) {
......@@ -849,22 +798,32 @@ static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst,
case 0:
REG_UPDATE(SYMCLKA_CLOCK_ENABLE,
SYMCLKA_CLOCK_ENABLE, 1);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, 1);
break;
case 1:
REG_UPDATE(SYMCLKB_CLOCK_ENABLE,
SYMCLKB_CLOCK_ENABLE, 1);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, 1);
break;
case 2:
REG_UPDATE(SYMCLKC_CLOCK_ENABLE,
SYMCLKC_CLOCK_ENABLE, 1);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, 1);
break;
case 3:
REG_UPDATE(SYMCLKD_CLOCK_ENABLE,
SYMCLKD_CLOCK_ENABLE, 1);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, 1);
break;
case 4:
REG_UPDATE(SYMCLKE_CLOCK_ENABLE,
SYMCLKE_CLOCK_ENABLE, 1);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, 1);
break;
}
......@@ -873,26 +832,36 @@ static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst,
REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
SYMCLKA_FE_EN, 1,
SYMCLKA_FE_SRC_SEL, link_enc_inst);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, 1);
break;
case 1:
REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
SYMCLKB_FE_EN, 1,
SYMCLKB_FE_SRC_SEL, link_enc_inst);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, 1);
break;
case 2:
REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
SYMCLKC_FE_EN, 1,
SYMCLKC_FE_SRC_SEL, link_enc_inst);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, 1);
break;
case 3:
REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
SYMCLKD_FE_EN, 1,
SYMCLKD_FE_SRC_SEL, link_enc_inst);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, 1);
break;
case 4:
REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,
SYMCLKE_FE_EN, 1,
SYMCLKE_FE_SRC_SEL, link_enc_inst);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, 1);
break;
}
}
......@@ -953,26 +922,36 @@ static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst
REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
SYMCLKA_FE_EN, 0,
SYMCLKA_FE_SRC_SEL, 0);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
// REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, 0);
break;
case 1:
REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
SYMCLKB_FE_EN, 0,
SYMCLKB_FE_SRC_SEL, 0);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
// REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, 0);
break;
case 2:
REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
SYMCLKC_FE_EN, 0,
SYMCLKC_FE_SRC_SEL, 0);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
// REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, 0);
break;
case 3:
REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
SYMCLKD_FE_EN, 0,
SYMCLKD_FE_SRC_SEL, 0);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
// REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, 0);
break;
case 4:
REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,
SYMCLKE_FE_EN, 0,
SYMCLKE_FE_SRC_SEL, 0);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
// REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, 0);
break;
}
......@@ -985,22 +964,32 @@ static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst
case 0:
REG_UPDATE(SYMCLKA_CLOCK_ENABLE,
SYMCLKA_CLOCK_ENABLE, 0);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
// REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, 0);
break;
case 1:
REG_UPDATE(SYMCLKB_CLOCK_ENABLE,
SYMCLKB_CLOCK_ENABLE, 0);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
// REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, 0);
break;
case 2:
REG_UPDATE(SYMCLKC_CLOCK_ENABLE,
SYMCLKC_CLOCK_ENABLE, 0);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
// REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, 0);
break;
case 3:
REG_UPDATE(SYMCLKD_CLOCK_ENABLE,
SYMCLKD_CLOCK_ENABLE, 0);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
// REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, 0);
break;
case 4:
REG_UPDATE(SYMCLKE_CLOCK_ENABLE,
SYMCLKE_CLOCK_ENABLE, 0);
// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
// REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, 0);
break;
}
}
......@@ -1033,7 +1022,6 @@ static const struct dccg_funcs dccg35_funcs = {
.set_valid_pixel_rate = dccg35_set_valid_pixel_rate,
.enable_symclk_se = dccg35_enable_symclk_se,
.disable_symclk_se = dccg35_disable_symclk_se,
.set_symclk_root_clock_gating = dccg35_set_symclk_root_clock_gating,
.set_dtbclk_p_src = dccg35_set_dtbclk_p_src,
};
......
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
View file @ 56116dc7
......@@ -519,17 +519,6 @@ void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_
}
}
void dcn35_symclk_root_clock_control(struct dce_hwseq *hws, unsigned int enc_inst, bool clock_on)
{
if (!hws->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
return;
if (hws->ctx->dc->res_pool->dccg->funcs->set_symclk_root_clock_gating) {
hws->ctx->dc->res_pool->dccg->funcs->set_symclk_root_clock_gating(
hws->ctx->dc->res_pool->dccg, enc_inst, enc_inst, clock_on);
}
}
void dcn35_dsc_pg_control(
struct dce_hwseq *hws,
unsigned int dsc_inst,
......@@ -1019,7 +1008,6 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
int i = 0, j = 0;
int edp_num = 0;
struct dc_link *edp_links[MAX_NUM_EDP] = { NULL };
bool stream_enc_in_use[MAX_PIPES] = { false };
memset(update_state, 0, sizeof(struct pg_block_update));
......@@ -1065,17 +1053,10 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
if (pipe_ctx->stream_res.hpo_dp_stream_enc)
update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;
if (pipe_ctx->stream_res.stream_enc &&
!pipe_ctx->stream_res.hpo_dp_stream_enc)
stream_enc_in_use[pipe_ctx->stream_res.stream_enc->stream_enc_inst] = true;
}
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (stream_enc_in_use[i])
update_state->pg_pipe_res_update[PG_SYMCLK][i] = false;
for (i = 0; i < dc->link_count; i++) {
update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;
if (dc->links[i]->type != dc_connection_none)
update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false;
}
......@@ -1139,10 +1120,6 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
if (j == PG_DPSTREAM && new_pipe->stream_res.hpo_dp_stream_enc)
update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;
if (j == PG_SYMCLK && new_pipe->stream_res.stream_enc &&
!new_pipe->stream_res.hpo_dp_stream_enc)
update_state->pg_pipe_res_update[j][new_pipe->stream_res.stream_enc->stream_enc_inst] = true;
}
} else if (cur_pipe->plane_state == new_pipe->plane_state ||
cur_pipe == new_pipe) {
......@@ -1177,12 +1154,6 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
cur_pipe->stream_res.hpo_dp_stream_enc != new_pipe->stream_res.hpo_dp_stream_enc &&
new_pipe->stream_res.hpo_dp_stream_enc)
update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;
if (j == PG_SYMCLK &&
new_pipe->stream_res.stream_enc &&
cur_pipe->stream_res.stream_enc != new_pipe->stream_res.stream_enc &&
!new_pipe->stream_res.hpo_dp_stream_enc)
update_state->pg_pipe_res_update[j][new_pipe->stream_res.stream_enc->stream_enc_inst] = true;
}
}
}
......@@ -1341,16 +1312,11 @@ void dcn35_root_clock_control(struct dc *dc,
dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);
}
for (i = 0; i < dc->res_pool->dig_link_enc_count; i++) {
for (i = 0; i < dc->res_pool->dig_link_enc_count; i++)
if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i])
if (dc->hwseq->funcs.physymclk_root_clock_control)
dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);
if (update_state->pg_pipe_res_update[PG_SYMCLK][i])
if (dc->hwseq->funcs.symclk_root_clock_control)
dc->hwseq->funcs.symclk_root_clock_control(dc->hwseq, i, power_on);
}
}
for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
if (update_state->pg_pipe_res_update[PG_DSC][i]) {
......@@ -1376,16 +1342,11 @@ void dcn35_root_clock_control(struct dc *dc,
dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);
}
for (i = 0; i < dc->res_pool->dig_link_enc_count; i++) {
for (i = 0; i < dc->res_pool->dig_link_enc_count; i++)
if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i])
if (dc->hwseq->funcs.physymclk_root_clock_control)
dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);
if (update_state->pg_pipe_res_update[PG_SYMCLK][i])
if (dc->hwseq->funcs.symclk_root_clock_control)
dc->hwseq->funcs.symclk_root_clock_control(dc->hwseq, i, power_on);
}
}
}
......
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
View file @ 56116dc7
......@@ -41,8 +41,6 @@ void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hp
void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on);
void dcn35_symclk_root_clock_control(struct dce_hwseq *hws, unsigned int enc_inst, bool clock_on);
void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);
......
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
View file @ 56116dc7
......@@ -150,7 +150,6 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {
.dpp_root_clock_control = dcn35_dpp_root_clock_control,
.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,
.symclk_root_clock_control = dcn35_symclk_root_clock_control,
.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
.update_odm = dcn35_update_odm,
.set_hdr_multiplier = dcn10_set_hdr_multiplier,
......
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
View file @ 56116dc7
......@@ -149,7 +149,6 @@ static const struct hwseq_private_funcs dcn351_private_funcs = {
.dpp_root_clock_control = dcn35_dpp_root_clock_control,
.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,
.symclk_root_clock_control = dcn35_symclk_root_clock_control,
.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
.update_odm = dcn35_update_odm,
.set_hdr_multiplier = dcn10_set_hdr_multiplier,
......
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
View file @ 56116dc7
......@@ -128,10 +128,6 @@ struct hwseq_private_funcs {
struct dce_hwseq *hws,
unsigned int phy_inst,
bool clock_on);
void (*symclk_root_clock_control)(
struct dce_hwseq *hws,
unsigned int enc_inst,
bool clock_on);
void (*dpp_pg_control)(struct dce_hwseq *hws,
unsigned int dpp_inst,
bool power_on);
......
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
View file @ 56116dc7
......@@ -199,13 +199,6 @@ struct dccg_funcs {
struct dccg *dccg,
uint32_t stream_enc_inst,
uint32_t link_enc_inst);
void (*set_symclk_root_clock_gating)(
struct dccg *dccg,
uint32_t stream_enc_inst,
uint32_t link_enc_inst,
bool enable);
void (*set_dp_dto)(
struct dccg *dccg,
const struct dp_dto_params *params);
......
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