Commit 56260cbf authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher

drm/amd/display: update dml input population function

Update dcn20_populate_dml_pipes_from_context to correctly handle odm
when no surface is provided.
Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3ebf1468
...@@ -1949,9 +1949,14 @@ int dcn20_populate_dml_pipes_from_context( ...@@ -1949,9 +1949,14 @@ int dcn20_populate_dml_pipes_from_context(
} }
pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
== res_ctx->pipe_ctx[i].plane_state) == res_ctx->pipe_ctx[i].plane_state) {
pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
== res_ctx->pipe_ctx[i].plane_state)
first_pipe = first_pipe->top_pipe;
pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
} else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
while (first_pipe->prev_odm_pipe) while (first_pipe->prev_odm_pipe)
...@@ -2046,6 +2051,7 @@ int dcn20_populate_dml_pipes_from_context( ...@@ -2046,6 +2051,7 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit; pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
if (!res_ctx->pipe_ctx[i].plane_state) { if (!res_ctx->pipe_ctx[i].plane_state) {
pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
pipes[pipe_cnt].pipe.src.source_scan = dm_horz; pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear; pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
...@@ -2071,19 +2077,21 @@ int dcn20_populate_dml_pipes_from_context( ...@@ -2071,19 +2077,21 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
pipes[pipe_cnt].pipe.scale_taps.htaps = 1; pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
pipes[pipe_cnt].pipe.src.is_hsplit = 0;
pipes[pipe_cnt].pipe.dest.odm_combine = 0;
pipes[pipe_cnt].pipe.dest.vtotal_min = v_total; pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
pipes[pipe_cnt].pipe.dest.vtotal_max = v_total; pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
pipes[pipe_cnt].pipe.src.viewport_width /= 2;
pipes[pipe_cnt].pipe.dest.recout_width /= 2;
}
} else { } else {
struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
&& res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
|| (res_ctx->pipe_ctx[i].top_pipe || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
&& res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
......
...@@ -112,6 +112,7 @@ struct _vcs_dpi_soc_bounding_box_st { ...@@ -112,6 +112,7 @@ struct _vcs_dpi_soc_bounding_box_st {
int use_urgent_burst_bw; int use_urgent_burst_bw;
unsigned int num_states; unsigned int num_states;
struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES]; struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES];
double min_dcfclk;
bool do_urgent_latency_adjustment; bool do_urgent_latency_adjustment;
double urgent_latency_adjustment_fabric_clock_component_us; double urgent_latency_adjustment_fabric_clock_component_us;
double urgent_latency_adjustment_fabric_clock_reference_mhz; double urgent_latency_adjustment_fabric_clock_reference_mhz;
......
...@@ -266,8 +266,6 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib) ...@@ -266,8 +266,6 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz; mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz;
mode_lib->vba.DTBCLKPerState[i] = soc->clock_limits[i].dtbclk_mhz; mode_lib->vba.DTBCLKPerState[i] = soc->clock_limits[i].dtbclk_mhz;
} }
mode_lib->vba.MinVoltageLevel = 0;
mode_lib->vba.MaxVoltageLevel = mode_lib->vba.soc.num_states;
mode_lib->vba.DoUrgentLatencyAdjustment = mode_lib->vba.DoUrgentLatencyAdjustment =
soc->do_urgent_latency_adjustment; soc->do_urgent_latency_adjustment;
......
...@@ -842,8 +842,6 @@ struct vba_vars_st { ...@@ -842,8 +842,6 @@ struct vba_vars_st {
double DCCRateChroma[DC__NUM_DPP__MAX]; double DCCRateChroma[DC__NUM_DPP__MAX];
double PHYCLKD18PerState[DC__VOLTAGE_STATES + 1]; double PHYCLKD18PerState[DC__VOLTAGE_STATES + 1];
int MinVoltageLevel;
int MaxVoltageLevel;
bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream; bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
bool NumberOfHDMIFRLSupport; bool NumberOfHDMIFRLSupport;
...@@ -880,7 +878,6 @@ struct vba_vars_st { ...@@ -880,7 +878,6 @@ struct vba_vars_st {
double TotalMetaRowBandwidth[DC__VOLTAGE_STATES + 1][2]; double TotalMetaRowBandwidth[DC__VOLTAGE_STATES + 1][2];
double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES + 1][2]; double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES + 1][2];
double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES + 1][2]; double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES + 1][2];
bool UseMinimumRequiredDCFCLK;
double WritebackDelayTime[DC__NUM_DPP__MAX]; double WritebackDelayTime[DC__NUM_DPP__MAX];
unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX]; unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX]; unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
......
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