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Commit 573f2035 authored by Eilon Greenstein's avatar Eilon Greenstein Committed by David S. Miller
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bnx2x: Re-factor the initialization code 

Moving the code to a more logical place and beautifying it. No real change in
behavior.
Signed-off-by: default avatarVladislav Zolotarov <vladz@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e4ed7113
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Showing with 495 additions and 464 deletions
drivers/net/bnx2x.h
View file @ 573f2035
......@@ -116,16 +116,22 @@
#define REG_RD_DMAE(bp, offset, valp, len32) \
do { \
bnx2x_read_dmae(bp, offset, len32);\
memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
} while (0)
#define REG_WR_DMAE(bp, offset, valp, len32) \
do { \
memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
offset, len32); \
} while (0)
#define VIRT_WR_DMAE_LEN(bp, data, addr, len32) \
do { \
memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
bnx2x_write_big_buf_wb(bp, addr, len32); \
} while (0)
#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
offsetof(struct shmem_region, field))
#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
......@@ -988,6 +994,9 @@ struct bnx2x {
dma_addr_t gunzip_mapping;
int gunzip_outlen;
#define FW_BUF_SIZE 0x8000
#define GUNZIP_BUF(bp) (bp->gunzip_buf)
#define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
struct raw_op *init_ops;
/* Init blocks offsets inside init_ops */
......@@ -1003,6 +1012,18 @@ struct bnx2x {
const u8 *xsem_pram_data;
const u8 *csem_int_table_data;
const u8 *csem_pram_data;
#define INIT_OPS(bp) (bp->init_ops)
#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
#define INIT_DATA(bp) (bp->init_data)
#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
const struct firmware *firmware;
};
......@@ -1030,6 +1051,9 @@ int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
u32 addr, u32 len);
static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
int wait)
......
drivers/net/bnx2x_init.h
View file @ 573f2035
This diff is collapsed.
drivers/net/bnx2x_init_ops.h
View file @ 573f2035
This diff is collapsed.
drivers/net/bnx2x_main.c
View file @ 573f2035
......@@ -153,7 +153,7 @@ MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
/* used only at init
* locking is done by mcp
*/
static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
{
pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
......@@ -346,6 +346,21 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
mutex_unlock(&bp->dmae_mutex);
}
void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
u32 addr, u32 len)
{
int offset = 0;
while (len > DMAE_LEN32_WR_MAX) {
bnx2x_write_dmae(bp, phys_addr + offset,
addr + offset, DMAE_LEN32_WR_MAX);
offset += DMAE_LEN32_WR_MAX * 4;
len -= DMAE_LEN32_WR_MAX;
}
bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
}
/* used only for slowpath so not inlined */
static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
{
......@@ -5917,6 +5932,24 @@ static void bnx2x_reset_common(struct bnx2x *bp)
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
}
static void bnx2x_init_pxp(struct bnx2x *bp)
{
u16 devctl;
int r_order, w_order;
pci_read_config_word(bp->pdev,
bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
if (bp->mrrs == -1)
r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
else {
DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
r_order = bp->mrrs;
}
bnx2x_init_pxp_arb(bp, r_order, w_order);
}
static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
{
......@@ -6479,9 +6512,15 @@ static int bnx2x_init_func(struct bnx2x *bp)
if (CHIP_IS_E1H(bp)) {
for (i = 0; i < 9; i++)
bnx2x_init_block(bp,
cm_blocks[i], FUNC0_STAGE + func);
bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
......@@ -11834,22 +11873,22 @@ static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev)
BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, be16_to_cpu_n);
/* STORMs firmware */
bp->tsem_int_table_data = bp->firmware->data +
be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
bp->tsem_pram_data = bp->firmware->data +
be32_to_cpu(fw_hdr->tsem_pram_data.offset);
bp->usem_int_table_data = bp->firmware->data +
be32_to_cpu(fw_hdr->usem_int_table_data.offset);
bp->usem_pram_data = bp->firmware->data +
be32_to_cpu(fw_hdr->usem_pram_data.offset);
bp->xsem_int_table_data = bp->firmware->data +
be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
bp->xsem_pram_data = bp->firmware->data +
be32_to_cpu(fw_hdr->xsem_pram_data.offset);
bp->csem_int_table_data = bp->firmware->data +
be32_to_cpu(fw_hdr->csem_int_table_data.offset);
bp->csem_pram_data = bp->firmware->data +
be32_to_cpu(fw_hdr->csem_pram_data.offset);
INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
be32_to_cpu(fw_hdr->tsem_pram_data.offset);
INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
be32_to_cpu(fw_hdr->usem_int_table_data.offset);
INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
be32_to_cpu(fw_hdr->usem_pram_data.offset);
INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
be32_to_cpu(fw_hdr->xsem_pram_data.offset);
INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
be32_to_cpu(fw_hdr->csem_int_table_data.offset);
INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
be32_to_cpu(fw_hdr->csem_pram_data.offset);
return 0;
init_offsets_alloc_err:
......
drivers/net/bnx2x_reg.h
View file @ 573f2035
......@@ -6019,3 +6019,116 @@ Theotherbitsarereservedandshouldbezero*/
#define COMMAND_REG_SIMD_NOMASK 0x1c
#define IGU_MEM_BASE 0x0000
#define IGU_MEM_MSIX_BASE 0x0000
#define IGU_MEM_MSIX_UPPER 0x007f
#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
#define IGU_MEM_PBA_MSIX_BASE 0x0200
#define IGU_MEM_PBA_MSIX_UPPER 0x0200
#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
#define IGU_CMD_INT_ACK_BASE 0x0400
#define IGU_CMD_INT_ACK_UPPER\
(IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
#define IGU_CMD_E2_PROD_UPD_BASE 0x0500
#define IGU_CMD_E2_PROD_UPD_UPPER\
(IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
#define IGU_REG_RESERVED_UPPER 0x05ff
#define CDU_REGION_NUMBER_XCM_AG 2
#define CDU_REGION_NUMBER_UCM_AG 4
/**
* String-to-compress [31:8] = CID (all 24 bits)
* String-to-compress [7:4] = Region
* String-to-compress [3:0] = Type
*/
#define CDU_VALID_DATA(_cid, _region, _type)\
(((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
#define CDU_CRC8(_cid, _region, _type)\
(calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
(0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
(0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
/******************************************************************************
* Description:
* Calculates crc 8 on a word value: polynomial 0-1-2-8
* Code was translated from Verilog.
* Return:
*****************************************************************************/
static inline u8 calc_crc8(u32 data, u8 crc)
{
u8 D[32];
u8 NewCRC[8];
u8 C[8];
u8 crc_res;
u8 i;
/* split the data into 31 bits */
for (i = 0; i < 32; i++) {
D[i] = (u8)(data & 1);
data = data >> 1;
}
/* split the crc into 8 bits */
for (i = 0; i < 8; i++) {
C[i] = crc & 1;
crc = crc >> 1;
}
NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
C[6] ^ C[7];
NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
C[6];
NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
C[0] ^ C[1] ^ C[4] ^ C[5];
NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
C[1] ^ C[2] ^ C[5] ^ C[6];
NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
C[3] ^ C[4] ^ C[7];
NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
C[5];
NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
C[6];
crc_res = 0;
for (i = 0; i < 8; i++)
crc_res |= (NewCRC[i] << i);
return crc_res;
}
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