Commit 577fb131 authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Chris Ball

mmc: rework selection of bus speed mode

Current implementation for bus speed mode selection is too
complicated. This patch is to simplify the codes and remove
some duplicate parts.

The following changes are including:
* Adds functions for each mode selection(HS, HS-DDR, HS200 and etc)
* Rearranged the mode selection sequence with supported device type
* Adds maximum speed for HS200 mode(hs200_max_dtr)
* Adds field definition for HS_TIMING of EXT_CSD
Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Tested-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
Acked-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent 2385049d
...@@ -139,7 +139,7 @@ static int mmc_ios_show(struct seq_file *s, void *data) ...@@ -139,7 +139,7 @@ static int mmc_ios_show(struct seq_file *s, void *data)
str = "mmc DDR52"; str = "mmc DDR52";
break; break;
case MMC_TIMING_MMC_HS200: case MMC_TIMING_MMC_HS200:
str = "mmc high-speed SDR200"; str = "mmc HS200";
break; break;
default: default:
str = "invalid"; str = "invalid";
......
This diff is collapsed.
...@@ -63,6 +63,7 @@ struct mmc_ext_csd { ...@@ -63,6 +63,7 @@ struct mmc_ext_csd {
unsigned int power_off_longtime; /* Units: ms */ unsigned int power_off_longtime; /* Units: ms */
u8 power_off_notification; /* state */ u8 power_off_notification; /* state */
unsigned int hs_max_dtr; unsigned int hs_max_dtr;
unsigned int hs200_max_dtr;
#define MMC_HIGH_26_MAX_DTR 26000000 #define MMC_HIGH_26_MAX_DTR 26000000
#define MMC_HIGH_52_MAX_DTR 52000000 #define MMC_HIGH_52_MAX_DTR 52000000
#define MMC_HIGH_DDR_MAX_DTR 52000000 #define MMC_HIGH_DDR_MAX_DTR 52000000
......
...@@ -377,6 +377,10 @@ struct _mmc_csd { ...@@ -377,6 +377,10 @@ struct _mmc_csd {
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
#define EXT_CSD_TIMING_HS 1 /* High speed */
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
#define EXT_CSD_SEC_ER_EN BIT(0) #define EXT_CSD_SEC_ER_EN BIT(0)
#define EXT_CSD_SEC_BD_BLK_EN BIT(2) #define EXT_CSD_SEC_BD_BLK_EN BIT(2)
#define EXT_CSD_SEC_GB_CL_EN BIT(4) #define EXT_CSD_SEC_GB_CL_EN BIT(4)
......
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