Commit 5780cf09 authored by Andrew Davis's avatar Andrew Davis Committed by Nishanth Menon

arm64: dts: ti: k3-am65: Enable EPWM nodes at the board level

EPWM nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.

As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the EPWM nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: default avatarAndrew Davis <afd@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Tested-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: default avatarBryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-5-afd@ti.com
parent 1c49cbb1
...@@ -886,6 +886,7 @@ ehrpwm0: pwm@3000000 { ...@@ -886,6 +886,7 @@ ehrpwm0: pwm@3000000 {
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
clock-names = "tbclk", "fck"; clock-names = "tbclk", "fck";
status = "disabled";
}; };
ehrpwm1: pwm@3010000 { ehrpwm1: pwm@3010000 {
...@@ -895,6 +896,7 @@ ehrpwm1: pwm@3010000 { ...@@ -895,6 +896,7 @@ ehrpwm1: pwm@3010000 {
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
clock-names = "tbclk", "fck"; clock-names = "tbclk", "fck";
status = "disabled";
}; };
ehrpwm2: pwm@3020000 { ehrpwm2: pwm@3020000 {
...@@ -904,6 +906,7 @@ ehrpwm2: pwm@3020000 { ...@@ -904,6 +906,7 @@ ehrpwm2: pwm@3020000 {
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
clock-names = "tbclk", "fck"; clock-names = "tbclk", "fck";
status = "disabled";
}; };
ehrpwm3: pwm@3030000 { ehrpwm3: pwm@3030000 {
...@@ -913,6 +916,7 @@ ehrpwm3: pwm@3030000 { ...@@ -913,6 +916,7 @@ ehrpwm3: pwm@3030000 {
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
clock-names = "tbclk", "fck"; clock-names = "tbclk", "fck";
status = "disabled";
}; };
ehrpwm4: pwm@3040000 { ehrpwm4: pwm@3040000 {
...@@ -922,6 +926,7 @@ ehrpwm4: pwm@3040000 { ...@@ -922,6 +926,7 @@ ehrpwm4: pwm@3040000 {
power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
clock-names = "tbclk", "fck"; clock-names = "tbclk", "fck";
status = "disabled";
}; };
ehrpwm5: pwm@3050000 { ehrpwm5: pwm@3050000 {
...@@ -931,6 +936,7 @@ ehrpwm5: pwm@3050000 { ...@@ -931,6 +936,7 @@ ehrpwm5: pwm@3050000 {
power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
clock-names = "tbclk", "fck"; clock-names = "tbclk", "fck";
status = "disabled";
}; };
icssg0: icssg@b000000 { icssg0: icssg@b000000 {
......
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