Commit 5886a96a authored by Oz Shlomo's avatar Oz Shlomo Committed by Saeed Mahameed

net/mlx5: Revise gre and nvgre key formats

GRE RFC defines a 32 bit key field. NVGRE RFC splits the 32 bit
key field to 24 bit VSID (gre_key_h) and 8 bit flow entropy (gre_key_l).

Define the two key parsing alternatives in a union, thus enabling both
access methods.
Signed-off-by: default avatarOz Shlomo <ozsh@mellanox.com>
Reviewed-by: default avatarEli Britstein <elibr@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent fd4572b3
...@@ -2680,11 +2680,11 @@ static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, ...@@ -2680,11 +2680,11 @@ static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
ntohs(ib_spec->gre.val.protocol)); ntohs(ib_spec->gre.val.protocol));
memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
gre_key_h), gre_key.nvgre.hi),
&ib_spec->gre.mask.key, &ib_spec->gre.mask.key,
sizeof(ib_spec->gre.mask.key)); sizeof(ib_spec->gre.mask.key));
memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v, memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
gre_key_h), gre_key.nvgre.hi),
&ib_spec->gre.val.key, &ib_spec->gre.val.key,
sizeof(ib_spec->gre.val.key)); sizeof(ib_spec->gre.val.key));
break; break;
......
...@@ -161,10 +161,10 @@ static void print_misc_parameters_hdrs(struct trace_seq *p, ...@@ -161,10 +161,10 @@ static void print_misc_parameters_hdrs(struct trace_seq *p,
PRINT_MASKED_VAL(name, p, format); \ PRINT_MASKED_VAL(name, p, format); \
} }
DECLARE_MASK_VAL(u64, gre_key) = { DECLARE_MASK_VAL(u64, gre_key) = {
.m = MLX5_GET(fte_match_set_misc, mask, gre_key_h) << 8 | .m = MLX5_GET(fte_match_set_misc, mask, gre_key.nvgre.hi) << 8 |
MLX5_GET(fte_match_set_misc, mask, gre_key_l), MLX5_GET(fte_match_set_misc, mask, gre_key.nvgre.lo),
.v = MLX5_GET(fte_match_set_misc, value, gre_key_h) << 8 | .v = MLX5_GET(fte_match_set_misc, value, gre_key.nvgre.hi) << 8 |
MLX5_GET(fte_match_set_misc, value, gre_key_l)}; MLX5_GET(fte_match_set_misc, value, gre_key.nvgre.lo)};
PRINT_MASKED_VAL(gre_key, p, "%llu"); PRINT_MASKED_VAL(gre_key, p, "%llu");
PRINT_MASKED_VAL_MISC(u32, source_sqn, source_sqn, p, "%u"); PRINT_MASKED_VAL_MISC(u32, source_sqn, source_sqn, p, "%u");
......
...@@ -423,6 +423,16 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits { ...@@ -423,6 +423,16 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
}; };
struct mlx5_ifc_nvgre_key_bits {
u8 hi[0x18];
u8 lo[0x8];
};
union mlx5_ifc_gre_key_bits {
struct mlx5_ifc_nvgre_key_bits nvgre;
u8 key[0x20];
};
struct mlx5_ifc_fte_match_set_misc_bits { struct mlx5_ifc_fte_match_set_misc_bits {
u8 reserved_at_0[0x8]; u8 reserved_at_0[0x8];
u8 source_sqn[0x18]; u8 source_sqn[0x18];
...@@ -444,8 +454,7 @@ struct mlx5_ifc_fte_match_set_misc_bits { ...@@ -444,8 +454,7 @@ struct mlx5_ifc_fte_match_set_misc_bits {
u8 reserved_at_64[0xc]; u8 reserved_at_64[0xc];
u8 gre_protocol[0x10]; u8 gre_protocol[0x10];
u8 gre_key_h[0x18]; union mlx5_ifc_gre_key_bits gre_key;
u8 gre_key_l[0x8];
u8 vxlan_vni[0x18]; u8 vxlan_vni[0x18];
u8 reserved_at_b8[0x8]; u8 reserved_at_b8[0x8];
......
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