Commit 58da3b42 authored by Rakesh Pillai's avatar Rakesh Pillai Committed by Kalle Valo

ath10k: skip resetting rx filter for WCN3990

WCN3990 has the MAC_PCU_ADDR1 configured properly
and hence it will not send spurious ack frames
during boot up.

Hence the reset_rx_filter workaround is not needed
for WCN3990. Add a hw_param to indicate if hardware rx
filter reset is needed and skip the reset_rx_filter for
WCN3990.

Tested HW: WCN3990
Tested FW: WLAN.HL.2.0-01188-QCAHLSWMTPLZ-1
Signed-off-by: default avatarRakesh Pillai <pillair@codeaurora.org>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent d410e28f
...@@ -91,6 +91,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -91,6 +91,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA988X_HW_2_0_VERSION, .id = QCA988X_HW_2_0_VERSION,
...@@ -124,6 +125,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -124,6 +125,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA9887_HW_1_0_VERSION, .id = QCA9887_HW_1_0_VERSION,
...@@ -157,6 +159,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -157,6 +159,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA6174_HW_2_1_VERSION, .id = QCA6174_HW_2_1_VERSION,
...@@ -189,6 +192,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -189,6 +192,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA6174_HW_2_1_VERSION, .id = QCA6174_HW_2_1_VERSION,
...@@ -221,6 +225,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -221,6 +225,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA6174_HW_3_0_VERSION, .id = QCA6174_HW_3_0_VERSION,
...@@ -253,6 +258,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -253,6 +258,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA6174_HW_3_2_VERSION, .id = QCA6174_HW_3_2_VERSION,
...@@ -288,6 +294,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -288,6 +294,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA99X0_HW_2_0_DEV_VERSION, .id = QCA99X0_HW_2_0_DEV_VERSION,
...@@ -326,6 +333,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -326,6 +333,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA9984_HW_1_0_DEV_VERSION, .id = QCA9984_HW_1_0_DEV_VERSION,
...@@ -369,6 +377,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -369,6 +377,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA9888_HW_2_0_DEV_VERSION, .id = QCA9888_HW_2_0_DEV_VERSION,
...@@ -411,6 +420,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -411,6 +420,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA9377_HW_1_0_DEV_VERSION, .id = QCA9377_HW_1_0_DEV_VERSION,
...@@ -443,6 +453,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -443,6 +453,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA9377_HW_1_1_DEV_VERSION, .id = QCA9377_HW_1_1_DEV_VERSION,
...@@ -477,6 +488,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -477,6 +488,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = QCA4019_HW_1_0_DEV_VERSION, .id = QCA4019_HW_1_0_DEV_VERSION,
...@@ -516,6 +528,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -516,6 +528,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false, .shadow_reg_support = false,
.rri_on_ddr = false, .rri_on_ddr = false,
.hw_filter_reset_required = true,
}, },
{ {
.id = WCN3990_HW_1_0_DEV_VERSION, .id = WCN3990_HW_1_0_DEV_VERSION,
...@@ -539,6 +552,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -539,6 +552,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.per_ce_irq = true, .per_ce_irq = true,
.shadow_reg_support = true, .shadow_reg_support = true,
.rri_on_ddr = true, .rri_on_ddr = true,
.hw_filter_reset_required = false,
}, },
}; };
...@@ -2405,7 +2419,8 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, ...@@ -2405,7 +2419,8 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
* possible to implicitly make it correct by creating a dummy vdev and * possible to implicitly make it correct by creating a dummy vdev and
* then deleting it. * then deleting it.
*/ */
if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { if (ar->hw_params.hw_filter_reset_required &&
mode == ATH10K_FIRMWARE_MODE_NORMAL) {
status = ath10k_core_reset_rx_filter(ar); status = ath10k_core_reset_rx_filter(ar);
if (status) { if (status) {
ath10k_err(ar, ath10k_err(ar,
......
...@@ -589,6 +589,11 @@ struct ath10k_hw_params { ...@@ -589,6 +589,11 @@ struct ath10k_hw_params {
/* Number of bytes to be the offset for each FFT sample */ /* Number of bytes to be the offset for each FFT sample */
int spectral_bin_offset; int spectral_bin_offset;
/* targets which require hw filter reset during boot up,
* to avoid it sending spurious acks.
*/
bool hw_filter_reset_required;
}; };
struct htt_rx_desc; struct htt_rx_desc;
......
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