Skip to content

L
linux
Commit 5a24b1fd authored by Peng Li's avatar Peng Li Committed by David S. Miller
Browse files
Options

net: hns3: merge some repetitive macros 

There are some repetitive macros have same meaning and value, this patch
merges them to make code clean.
Signed-off-by: default avatarPeng Li <lipeng321@huawei.com>
Signed-off-by: default avatarGuangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d7517f8f
Hide whitespace changes
Inline Side-by-side
Showing with 44 additions and 63 deletions
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
View file @ 5a24b1fd
...@@ -1017,16 +1017,6 @@ struct hclge_common_lb_cmd { ...@@ -1017,16 +1017,6 @@ struct hclge_common_lb_cmd {
#define HCLGE_TYPE_CRQ 0 #define HCLGE_TYPE_CRQ 0
#define HCLGE_TYPE_CSQ 1 #define HCLGE_TYPE_CSQ 1
#define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
#define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
#define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
#define HCLGE_NIC_CSQ_TAIL_REG 0x27010
#define HCLGE_NIC_CSQ_HEAD_REG 0x27014
#define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
#define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
#define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
#define HCLGE_NIC_CRQ_TAIL_REG 0x27024
#define HCLGE_NIC_CRQ_HEAD_REG 0x27028
/* this bit indicates that the driver is ready for hardware reset */ /* this bit indicates that the driver is ready for hardware reset */
#define HCLGE_NIC_SW_RST_RDY_B 16 #define HCLGE_NIC_SW_RST_RDY_B 16
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
View file @ 5a24b1fd
...@@ -92,23 +92,23 @@ static const struct pci_device_id ae_algo_pci_tbl[] = { ...@@ -92,23 +92,23 @@ static const struct pci_device_id ae_algo_pci_tbl[] = {
MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
static const u32 cmdq_reg_addr_list[] = {HCLGE_CMDQ_TX_ADDR_L_REG, static const u32 cmdq_reg_addr_list[] = {HCLGE_NIC_CSQ_BASEADDR_L_REG,
HCLGE_CMDQ_TX_ADDR_H_REG, HCLGE_NIC_CSQ_BASEADDR_H_REG,
HCLGE_CMDQ_TX_DEPTH_REG, HCLGE_NIC_CSQ_DEPTH_REG,
HCLGE_CMDQ_TX_TAIL_REG, HCLGE_NIC_CSQ_TAIL_REG,
HCLGE_CMDQ_TX_HEAD_REG, HCLGE_NIC_CSQ_HEAD_REG,
HCLGE_CMDQ_RX_ADDR_L_REG, HCLGE_NIC_CRQ_BASEADDR_L_REG,
HCLGE_CMDQ_RX_ADDR_H_REG, HCLGE_NIC_CRQ_BASEADDR_H_REG,
HCLGE_CMDQ_RX_DEPTH_REG, HCLGE_NIC_CRQ_DEPTH_REG,
HCLGE_CMDQ_RX_TAIL_REG, HCLGE_NIC_CRQ_TAIL_REG,
HCLGE_CMDQ_RX_HEAD_REG, HCLGE_NIC_CRQ_HEAD_REG,
HCLGE_VECTOR0_CMDQ_SRC_REG, HCLGE_VECTOR0_CMDQ_SRC_REG,
HCLGE_CMDQ_INTR_STS_REG, HCLGE_CMDQ_INTR_STS_REG,
HCLGE_CMDQ_INTR_EN_REG, HCLGE_CMDQ_INTR_EN_REG,
HCLGE_CMDQ_INTR_GEN_REG}; HCLGE_CMDQ_INTR_GEN_REG};
static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE, static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
HCLGE_VECTOR0_OTER_EN_REG, HCLGE_PF_OTHER_INT_REG,
HCLGE_MISC_RESET_STS_REG, HCLGE_MISC_RESET_STS_REG,
HCLGE_MISC_VECTOR_INT_STS, HCLGE_MISC_VECTOR_INT_STS,
HCLGE_GLOBAL_RESET_REG, HCLGE_GLOBAL_RESET_REG,
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
View file @ 5a24b1fd
...@@ -38,22 +38,22 @@ ...@@ -38,22 +38,22 @@
#define HCLGE_VECTOR_REG_OFFSET_H 0x1000 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000
#define HCLGE_VECTOR_VF_OFFSET 0x100000 #define HCLGE_VECTOR_VF_OFFSET 0x100000
#define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
#define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
#define HCLGE_CMDQ_TX_DEPTH_REG 0x27008 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
#define HCLGE_CMDQ_TX_TAIL_REG 0x27010 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
#define HCLGE_CMDQ_TX_HEAD_REG 0x27014 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
#define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
#define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701C
#define HCLGE_CMDQ_RX_DEPTH_REG 0x27020 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
#define HCLGE_CMDQ_RX_TAIL_REG 0x27024 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
#define HCLGE_CMDQ_RX_HEAD_REG 0x27028 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
#define HCLGE_CMDQ_INTR_STS_REG 0x27104 #define HCLGE_CMDQ_INTR_STS_REG 0x27104
#define HCLGE_CMDQ_INTR_EN_REG 0x27108 #define HCLGE_CMDQ_INTR_EN_REG 0x27108
#define HCLGE_CMDQ_INTR_GEN_REG 0x2710C #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C
/* bar registers for common func */ /* bar registers for common func */
#define HCLGE_VECTOR0_OTER_EN_REG 0x20600
#define HCLGE_GRO_EN_REG 0x28000 #define HCLGE_GRO_EN_REG 0x28000
#define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008
......
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
View file @ 5a24b1fd
...@@ -266,16 +266,6 @@ struct hclgevf_cfg_tx_queue_pointer_cmd { ...@@ -266,16 +266,6 @@ struct hclgevf_cfg_tx_queue_pointer_cmd {
#define HCLGEVF_TYPE_CRQ 0 #define HCLGEVF_TYPE_CRQ 0
#define HCLGEVF_TYPE_CSQ 1 #define HCLGEVF_TYPE_CSQ 1
#define HCLGEVF_NIC_CSQ_BASEADDR_L_REG 0x27000
#define HCLGEVF_NIC_CSQ_BASEADDR_H_REG 0x27004
#define HCLGEVF_NIC_CSQ_DEPTH_REG 0x27008
#define HCLGEVF_NIC_CSQ_TAIL_REG 0x27010
#define HCLGEVF_NIC_CSQ_HEAD_REG 0x27014
#define HCLGEVF_NIC_CRQ_BASEADDR_L_REG 0x27018
#define HCLGEVF_NIC_CRQ_BASEADDR_H_REG 0x2701c
#define HCLGEVF_NIC_CRQ_DEPTH_REG 0x27020
#define HCLGEVF_NIC_CRQ_TAIL_REG 0x27024
#define HCLGEVF_NIC_CRQ_HEAD_REG 0x27028
/* this bit indicates that the driver is ready for hardware reset */ /* this bit indicates that the driver is ready for hardware reset */
#define HCLGEVF_NIC_SW_RST_RDY_B 16 #define HCLGEVF_NIC_SW_RST_RDY_B 16
......
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
View file @ 5a24b1fd
...@@ -40,16 +40,16 @@ static const u8 hclgevf_hash_key[] = { ...@@ -40,16 +40,16 @@ static const u8 hclgevf_hash_key[] = {
MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, static const u32 cmdq_reg_addr_list[] = {HCLGEVF_NIC_CSQ_BASEADDR_L_REG,
HCLGEVF_CMDQ_TX_ADDR_H_REG, HCLGEVF_NIC_CSQ_BASEADDR_H_REG,
HCLGEVF_CMDQ_TX_DEPTH_REG, HCLGEVF_NIC_CSQ_DEPTH_REG,
HCLGEVF_CMDQ_TX_TAIL_REG, HCLGEVF_NIC_CSQ_TAIL_REG,
HCLGEVF_CMDQ_TX_HEAD_REG, HCLGEVF_NIC_CSQ_HEAD_REG,
HCLGEVF_CMDQ_RX_ADDR_L_REG, HCLGEVF_NIC_CRQ_BASEADDR_L_REG,
HCLGEVF_CMDQ_RX_ADDR_H_REG, HCLGEVF_NIC_CRQ_BASEADDR_H_REG,
HCLGEVF_CMDQ_RX_DEPTH_REG, HCLGEVF_NIC_CRQ_DEPTH_REG,
HCLGEVF_CMDQ_RX_TAIL_REG, HCLGEVF_NIC_CRQ_TAIL_REG,
HCLGEVF_CMDQ_RX_HEAD_REG, HCLGEVF_NIC_CRQ_HEAD_REG,
HCLGEVF_VECTOR0_CMDQ_SRC_REG, HCLGEVF_VECTOR0_CMDQ_SRC_REG,
HCLGEVF_VECTOR0_CMDQ_STATE_REG, HCLGEVF_VECTOR0_CMDQ_STATE_REG,
HCLGEVF_CMDQ_INTR_EN_REG, HCLGEVF_CMDQ_INTR_EN_REG,
...@@ -1963,7 +1963,7 @@ static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) ...@@ -1963,7 +1963,7 @@ static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG));
dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
......
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
View file @ 5a24b1fd
...@@ -33,16 +33,17 @@ ...@@ -33,16 +33,17 @@
#define HCLGEVF_VECTOR_VF_OFFSET 0x100000 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000
/* bar registers for cmdq */ /* bar registers for cmdq */
#define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000 #define HCLGEVF_NIC_CSQ_BASEADDR_L_REG 0x27000
#define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004 #define HCLGEVF_NIC_CSQ_BASEADDR_H_REG 0x27004
#define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008 #define HCLGEVF_NIC_CSQ_DEPTH_REG 0x27008
#define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010 #define HCLGEVF_NIC_CSQ_TAIL_REG 0x27010
#define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014 #define HCLGEVF_NIC_CSQ_HEAD_REG 0x27014
#define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018 #define HCLGEVF_NIC_CRQ_BASEADDR_L_REG 0x27018
#define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C #define HCLGEVF_NIC_CRQ_BASEADDR_H_REG 0x2701C
#define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020 #define HCLGEVF_NIC_CRQ_DEPTH_REG 0x27020
#define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024 #define HCLGEVF_NIC_CRQ_TAIL_REG 0x27024
#define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028 #define HCLGEVF_NIC_CRQ_HEAD_REG 0x27028
#define HCLGEVF_CMDQ_INTR_EN_REG 0x27108 #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108
#define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7