Commit 5c932d16 authored by Vinod Koul's avatar Vinod Koul

Merge tag 'ti-serdes-for-5.13' into next

TI Serdes changes for 5.13
parents d9de0cbd 4709b21a
...@@ -28,13 +28,27 @@ properties: ...@@ -28,13 +28,27 @@ properties:
'#size-cells': '#size-cells':
const: 0 const: 0
'#clock-cells':
const: 1
clocks: clocks:
maxItems: 1 minItems: 1
maxItems: 2
description: description:
PHY reference clock. Must contain an entry in clock-names. PHY reference clock for 1 item. Must contain an entry in clock-names.
Optional Parent to enable output reference clock.
clock-names: clock-names:
const: refclk minItems: 1
items:
- const: refclk
- const: phy_en_refclk
assigned-clocks:
maxItems: 3
assigned-clock-parents:
maxItems: 3
reg: reg:
minItems: 1 minItems: 1
......
...@@ -15,6 +15,7 @@ properties: ...@@ -15,6 +15,7 @@ properties:
enum: enum:
- ti,j721e-wiz-16g - ti,j721e-wiz-16g
- ti,j721e-wiz-10g - ti,j721e-wiz-10g
- ti,am64-wiz-10g
power-domains: power-domains:
maxItems: 1 maxItems: 1
...@@ -42,6 +43,9 @@ properties: ...@@ -42,6 +43,9 @@ properties:
"#reset-cells": "#reset-cells":
const: 1 const: 1
"#clock-cells":
const: 1
ranges: true ranges: true
assigned-clocks: assigned-clocks:
......
...@@ -90,4 +90,9 @@ ...@@ -90,4 +90,9 @@
#define J7200_SERDES0_LANE3_USB 0x2 #define J7200_SERDES0_LANE3_USB 0x2
#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
/* AM64 */
#define AM64_SERDES0_LANE0_PCIE0 0x0
#define AM64_SERDES0_LANE0_USB 0x1
#endif /* _DT_BINDINGS_MUX_TI_SERDES */ #endif /* _DT_BINDINGS_MUX_TI_SERDES */
...@@ -10,4 +10,6 @@ ...@@ -10,4 +10,6 @@
#define TORRENT_SERDES_EXTERNAL_SSC 1 #define TORRENT_SERDES_EXTERNAL_SSC 1
#define TORRENT_SERDES_INTERNAL_SSC 2 #define TORRENT_SERDES_INTERNAL_SSC 2
#define CDNS_TORRENT_REFCLK_DRIVER 0
#endif /* _DT_BINDINGS_TORRENT_SERDES_H */ #endif /* _DT_BINDINGS_TORRENT_SERDES_H */
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for TI SERDES.
*/
#ifndef _DT_BINDINGS_TI_SERDES
#define _DT_BINDINGS_TI_SERDES
/* Clock index for output clocks from WIZ */
/* MUX Clocks */
#define TI_WIZ_PLL0_REFCLK 0
#define TI_WIZ_PLL1_REFCLK 1
#define TI_WIZ_REFCLK_DIG 2
/* Reserve index here for future additions */
/* MISC Clocks */
#define TI_WIZ_PHY_EN_REFCLK 16
#endif /* _DT_BINDINGS_TI_SERDES */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment