drm/amdgpu: fix handling order in scheduler CS

We need to clear parser.ibs and num_ibs before amd_sched_fence_create,
otherwise the IB could be freed twice if fence creates fails.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

@@ -858,11 +858,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 		job->base.sched = &ring->sched;
 		job->base.s_entity = &parser.ctx->rings[ring->idx].entity;
 		job->adev = parser.adev;
-		job->ibs = parser.ibs;
-		job->num_ibs = parser.num_ibs;
 		job->owner = parser.filp;
 		job->free_job = amdgpu_cs_free_job;
 
+		job->ibs = parser.ibs;
+		job->num_ibs = parser.num_ibs;
+		parser.ibs = NULL;
+		parser.num_ibs = 0;
+
 		if (job->ibs[job->num_ibs - 1].user) {
 			job->uf = parser.uf;
 			job->ibs[job->num_ibs - 1].user = &job->uf;
@@ -884,9 +887,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 						      &fence->base);
 		job->ibs[job->num_ibs - 1].sequence = cs->out.handle;
 
-		parser.ibs = NULL;
-		parser.num_ibs = 0;
-
 		trace_amdgpu_cs_ioctl(job);
 		amd_sched_entity_push_job(&job->base);