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Commit 5e1dd4f2 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events: Update Intel tigerlake 

Update to v1.07, the metrics are based on TMA 4.4 full.

Use script at:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py

to download and generate the latest events and metrics. Manually copy
the tigerlake files into perf and update mapfile.csv.

Tested on a non-tigerlake with 'perf test':
 10: PMU events                                                      :
 10.1: PMU event table sanity                                        : Ok
 10.2: PMU event map aliases                                         : Ok
 10.3: Parsing of PMU event table metrics                            : Ok
 10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20220727220832.2865794-27-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 59fd7d32
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Showing with 439 additions and 67 deletions
tools/perf/pmu-events/arch/x86/mapfile.csv
View file @ 5e1dd4f2
......@@ -24,10 +24,10 @@ GenuineIntel-6-8F,v1.04,sapphirerapids,core
GenuineIntel-6-(37|4C|4D),v14,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core
GenuineIntel-6-55-[01234],v1.28,skylakex,core
GenuineIntel-6-8[CD],v1.07,tigerlake,core
GenuineIntel-6-2C,v2,westmereep-dp,core
GenuineIntel-6-25,v2,westmereep-sp,core
GenuineIntel-6-2F,v2,westmereex,core
GenuineIntel-6-8[CD],v1,tigerlake,core
GenuineIntel-6-86,v1,snowridgex,core
AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core
AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core
......
tools/perf/pmu-events/arch/x86/tigerlake/cache.json
View file @ 5e1dd4f2
......@@ -112,6 +112,17 @@
"SampleAfterValue": "200003",
"UMask": "0xe4"
},
{
"BriefDescription": "Demand Data Read access L2 cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
"SampleAfterValue": "200003",
"UMask": "0xe1"
},
{
"BriefDescription": "RFO requests to L2 cache",
"CollectPEBSRecord": "2",
......@@ -157,16 +168,38 @@
"UMask": "0xc1"
},
{
"BriefDescription": "All requests that miss L2 cache",
"BriefDescription": "Demand Data Read miss L2 cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
"SampleAfterValue": "200003",
"UMask": "0x21"
},
{
"BriefDescription": "Read requests with true-miss in L2 cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all requests that miss L2 cache.",
"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.",
"SampleAfterValue": "200003",
"UMask": "0x3f"
},
{
"BriefDescription": "All accesses to L2 cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.",
"SampleAfterValue": "200003",
"UMask": "0xff"
},
{
"BriefDescription": "RFO requests that hit L2 cache",
"CollectPEBSRecord": "2",
......@@ -353,7 +386,7 @@
"UMask": "0x12"
},
{
"BriefDescription": "TBD",
"BriefDescription": "Snoop hit a modified(HITM) or clean line(HIT_W_FWD) in another on-pkg core which forwarded the data back due to a retired load instruction.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
......@@ -361,6 +394,7 @@
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions where a cross-core snoop hit in another cores caches on this socket, the data was forwarded back to the requesting core as the data was modified (SNOOP_HITM) or the L3 did not have the data(SNOOP_HIT_WITH_FWD).",
"SampleAfterValue": "20011",
"UMask": "0x4"
},
......@@ -391,7 +425,7 @@
"UMask": "0x8"
},
{
"BriefDescription": "TBD",
"BriefDescription": "Snoop hit without forwarding in another on-pkg core due to a retired load instruction, data was supplied by the L3.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
......@@ -399,6 +433,7 @@
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions in which the L3 supplied the data and a cross-core snoop hit in another cores caches on this socket but that other core did not forward the data back (SNOOP_HIT_NO_FWD).",
"SampleAfterValue": "20011",
"UMask": "0x2"
},
......@@ -503,7 +538,6 @@
"MSRValue": "0x10003C0001",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -517,7 +551,6 @@
"MSRValue": "0x8003C0001",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -531,7 +564,6 @@
"MSRValue": "0x10003C0002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -714,4 +746,4 @@
"SampleAfterValue": "100003",
"UMask": "0x4"
}
]
\ No newline at end of file
]
tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json
View file @ 5e1dd4f2
......@@ -98,4 +98,4 @@
"SampleAfterValue": "100003",
"UMask": "0x2"
}
]
\ No newline at end of file
]
tools/perf/pmu-events/arch/x86/tigerlake/frontend.json
View file @ 5e1dd4f2
......@@ -475,4 +475,4 @@
"SampleAfterValue": "1000003",
"UMask": "0x1"
}
]
\ No newline at end of file
]
tools/perf/pmu-events/arch/x86/tigerlake/memory.json
View file @ 5e1dd4f2
......@@ -292,4 +292,4 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
}
]
\ No newline at end of file
]
tools/perf/pmu-events/arch/x86/tigerlake/other.json
View file @ 5e1dd4f2
......@@ -42,7 +42,6 @@
"MSRValue": "0x10800",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
......
tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
View file @ 5e1dd4f2
......@@ -432,13 +432,13 @@
"UMask": "0x40"
},
{
"BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
"BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
"PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.",
"SampleAfterValue": "1000003",
"UMask": "0x80"
},
......
tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json 0 → 100644
View file @ 5e1dd4f2
[
{
"BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
"CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
"PublicDescription": "UNC_ARB_TRK_OCCUPANCY.ALL",
"UMask": "0x01",
"Unit": "ARB"
},
{
"BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
"Counter": "1",
"CounterType": "FREERUN",
"EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
"PerPkg": "1",
"PublicDescription": "UNC_MC0_RDCAS_COUNT_FREERUN",
"Unit": "h_imc"
},
{
"BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
"CounterType": "FREERUN",
"EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
"PerPkg": "1",
"PublicDescription": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
"Unit": "h_imc"
},
{
"BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
"Counter": "2",
"CounterType": "FREERUN",
"EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
"PerPkg": "1",
"PublicDescription": "UNC_MC0_WRCAS_COUNT_FREERUN",
"Unit": "h_imc"
},
{
"BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
"Counter": "4",
"CounterType": "FREERUN",
"EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
"PerPkg": "1",
"PublicDescription": "UNC_MC1_RDCAS_COUNT_FREERUN",
"Unit": "h_imc"
},
{
"BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
"Counter": "3",
"CounterType": "FREERUN",
"EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
"PerPkg": "1",
"PublicDescription": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
"Unit": "h_imc"
},
{
"BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
"Counter": "5",
"CounterType": "FREERUN",
"EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
"PerPkg": "1",
"PublicDescription": "UNC_MC1_WRCAS_COUNT_FREERUN",
"Unit": "h_imc"
}
]
tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json
View file @ 5e1dd4f2
......@@ -222,4 +222,4 @@
"SampleAfterValue": "100007",
"UMask": "0x20"
}
]
\ No newline at end of file
]
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