Commit 5e6d9fc7 authored by Rahul Verma's avatar Rahul Verma Committed by David S. Miller

qed: Add new ethtool supported port types based on media.

Supported ports in ethtool <eth1> are displayed based on media type.
For media type fibre and twinaxial, port type is "FIBRE". Media type
Base-T is "TP" and media KR is "Backplane".

V1->V2:
Corrected the subject.
Signed-off-by: default avatarRahul Verma <rahulv@marvell.com>
Signed-off-by: default avatarMichal Kalderon <michal.kalderon@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ad2dcba0
...@@ -1688,6 +1688,7 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn, ...@@ -1688,6 +1688,7 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn,
switch (media_type) { switch (media_type) {
case MEDIA_DA_TWINAX: case MEDIA_DA_TWINAX:
*if_capability |= QED_LM_FIBRE_BIT;
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
*if_capability |= QED_LM_20000baseKR2_Full_BIT; *if_capability |= QED_LM_20000baseKR2_Full_BIT;
/* For DAC media multiple speed capabilities are supported*/ /* For DAC media multiple speed capabilities are supported*/
...@@ -1707,6 +1708,7 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn, ...@@ -1707,6 +1708,7 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn,
*if_capability |= QED_LM_100000baseCR4_Full_BIT; *if_capability |= QED_LM_100000baseCR4_Full_BIT;
break; break;
case MEDIA_BASE_T: case MEDIA_BASE_T:
*if_capability |= QED_LM_TP_BIT;
if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) { if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) {
if (capability & if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) { NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
...@@ -1718,6 +1720,7 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn, ...@@ -1718,6 +1720,7 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn,
} }
} }
if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) { if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) {
*if_capability |= QED_LM_FIBRE_BIT;
if (tcvr_type == ETH_TRANSCEIVER_TYPE_1000BASET) if (tcvr_type == ETH_TRANSCEIVER_TYPE_1000BASET)
*if_capability |= QED_LM_1000baseT_Full_BIT; *if_capability |= QED_LM_1000baseT_Full_BIT;
if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_BASET) if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_BASET)
...@@ -1728,6 +1731,7 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn, ...@@ -1728,6 +1731,7 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn,
case MEDIA_SFPP_10G_FIBER: case MEDIA_SFPP_10G_FIBER:
case MEDIA_XFP_FIBER: case MEDIA_XFP_FIBER:
case MEDIA_MODULE_FIBER: case MEDIA_MODULE_FIBER:
*if_capability |= QED_LM_FIBRE_BIT;
if (capability & if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) { NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
if ((tcvr_type == ETH_TRANSCEIVER_TYPE_1G_LX) || if ((tcvr_type == ETH_TRANSCEIVER_TYPE_1G_LX) ||
...@@ -1770,6 +1774,7 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn, ...@@ -1770,6 +1774,7 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn,
break; break;
case MEDIA_KR: case MEDIA_KR:
*if_capability |= QED_LM_Backplane_BIT;
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
*if_capability |= QED_LM_20000baseKR2_Full_BIT; *if_capability |= QED_LM_20000baseKR2_Full_BIT;
if (capability & if (capability &
...@@ -1821,7 +1826,6 @@ static void qed_fill_link(struct qed_hwfn *hwfn, ...@@ -1821,7 +1826,6 @@ static void qed_fill_link(struct qed_hwfn *hwfn,
if_link->link_up = true; if_link->link_up = true;
/* TODO - at the moment assume supported and advertised speed equal */ /* TODO - at the moment assume supported and advertised speed equal */
if_link->supported_caps = QED_LM_FIBRE_BIT;
if (link_caps.default_speed_autoneg) if (link_caps.default_speed_autoneg)
if_link->supported_caps |= QED_LM_Autoneg_BIT; if_link->supported_caps |= QED_LM_Autoneg_BIT;
if (params.pause.autoneg || if (params.pause.autoneg ||
......
...@@ -424,12 +424,13 @@ struct qede_link_mode_mapping { ...@@ -424,12 +424,13 @@ struct qede_link_mode_mapping {
}; };
static const struct qede_link_mode_mapping qed_lm_map[] = { static const struct qede_link_mode_mapping qed_lm_map[] = {
{QED_LM_FIBRE_BIT, ETHTOOL_LINK_MODE_FIBRE_BIT},
{QED_LM_Autoneg_BIT, ETHTOOL_LINK_MODE_Autoneg_BIT}, {QED_LM_Autoneg_BIT, ETHTOOL_LINK_MODE_Autoneg_BIT},
{QED_LM_Asym_Pause_BIT, ETHTOOL_LINK_MODE_Asym_Pause_BIT}, {QED_LM_Asym_Pause_BIT, ETHTOOL_LINK_MODE_Asym_Pause_BIT},
{QED_LM_Pause_BIT, ETHTOOL_LINK_MODE_Pause_BIT}, {QED_LM_Pause_BIT, ETHTOOL_LINK_MODE_Pause_BIT},
{QED_LM_1000baseT_Full_BIT, ETHTOOL_LINK_MODE_1000baseT_Full_BIT}, {QED_LM_1000baseT_Full_BIT, ETHTOOL_LINK_MODE_1000baseT_Full_BIT},
{QED_LM_10000baseT_Full_BIT, ETHTOOL_LINK_MODE_10000baseT_Full_BIT}, {QED_LM_10000baseT_Full_BIT, ETHTOOL_LINK_MODE_10000baseT_Full_BIT},
{QED_LM_2500baseX_Full_BIT, ETHTOOL_LINK_MODE_2500baseX_Full_BIT}, {QED_LM_TP_BIT, ETHTOOL_LINK_MODE_TP_BIT},
{QED_LM_Backplane_BIT, ETHTOOL_LINK_MODE_Backplane_BIT}, {QED_LM_Backplane_BIT, ETHTOOL_LINK_MODE_Backplane_BIT},
{QED_LM_1000baseKX_Full_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT}, {QED_LM_1000baseKX_Full_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT},
{QED_LM_10000baseKX4_Full_BIT, ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT}, {QED_LM_10000baseKX4_Full_BIT, ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT},
......
...@@ -689,7 +689,7 @@ enum qed_link_mode_bits { ...@@ -689,7 +689,7 @@ enum qed_link_mode_bits {
QED_LM_40000baseLR4_Full_BIT = BIT(9), QED_LM_40000baseLR4_Full_BIT = BIT(9),
QED_LM_50000baseKR2_Full_BIT = BIT(10), QED_LM_50000baseKR2_Full_BIT = BIT(10),
QED_LM_100000baseKR4_Full_BIT = BIT(11), QED_LM_100000baseKR4_Full_BIT = BIT(11),
QED_LM_2500baseX_Full_BIT = BIT(12), QED_LM_TP_BIT = BIT(12),
QED_LM_Backplane_BIT = BIT(13), QED_LM_Backplane_BIT = BIT(13),
QED_LM_1000baseKX_Full_BIT = BIT(14), QED_LM_1000baseKX_Full_BIT = BIT(14),
QED_LM_10000baseKX4_Full_BIT = BIT(15), QED_LM_10000baseKX4_Full_BIT = BIT(15),
......
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