Commit 5fe8321b authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'x86-x2apic-for-linus' of...

Merge branch 'x86-x2apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-x2apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, x2apic: Simplify apic init in SMP and UP builds
  x86, intr-remap: Remove IRTE setup duplicate code
  x86, intr-remap: Set redirection hint in the IRTE
parents 709d9f54 fa47f7e5
...@@ -3,4 +3,31 @@ ...@@ -3,4 +3,31 @@
#define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8) #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
#ifdef CONFIG_INTR_REMAP
static inline void prepare_irte(struct irte *irte, int vector,
unsigned int dest)
{
memset(irte, 0, sizeof(*irte));
irte->present = 1;
irte->dst_mode = apic->irq_dest_mode;
/*
* Trigger mode in the IRTE will always be edge, and for IO-APIC, the
* actual level or edge trigger will be setup in the IO-APIC
* RTE. This will help simplify level triggered irq migration.
* For more details, see the comments (in io_apic.c) explainig IO-APIC
* irq migration in the presence of interrupt-remapping.
*/
irte->trigger_mode = 0;
irte->dlvry_mode = apic->irq_delivery_mode;
irte->vector = vector;
irte->dest_id = IRTE_DEST(dest);
irte->redir_hint = 1;
}
#else
static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
{
}
#endif
#endif /* _ASM_X86_IRQ_REMAPPING_H */ #endif /* _ASM_X86_IRQ_REMAPPING_H */
...@@ -1665,10 +1665,7 @@ int __init APIC_init_uniprocessor(void) ...@@ -1665,10 +1665,7 @@ int __init APIC_init_uniprocessor(void)
} }
#endif #endif
#ifndef CONFIG_SMP
enable_IR_x2apic();
default_setup_apic_routing(); default_setup_apic_routing();
#endif
verify_local_APIC(); verify_local_APIC();
connect_bsp_APIC(); connect_bsp_APIC();
......
...@@ -1382,21 +1382,7 @@ int setup_ioapic_entry(int apic_id, int irq, ...@@ -1382,21 +1382,7 @@ int setup_ioapic_entry(int apic_id, int irq,
if (index < 0) if (index < 0)
panic("Failed to allocate IRTE for ioapic %d\n", apic_id); panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
memset(&irte, 0, sizeof(irte)); prepare_irte(&irte, vector, destination);
irte.present = 1;
irte.dst_mode = apic->irq_dest_mode;
/*
* Trigger mode in the IRTE will always be edge, and the
* actual level or edge trigger will be setup in the IO-APIC
* RTE. This will help simplify level triggered irq migration.
* For more details, see the comments above explainig IO-APIC
* irq migration in the presence of interrupt-remapping.
*/
irte.trigger_mode = 0;
irte.dlvry_mode = apic->irq_delivery_mode;
irte.vector = vector;
irte.dest_id = IRTE_DEST(destination);
/* Set source-id of interrupt request */ /* Set source-id of interrupt request */
set_ioapic_sid(&irte, apic_id); set_ioapic_sid(&irte, apic_id);
...@@ -3340,14 +3326,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, ...@@ -3340,14 +3326,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
ir_index = map_irq_to_irte_handle(irq, &sub_handle); ir_index = map_irq_to_irte_handle(irq, &sub_handle);
BUG_ON(ir_index == -1); BUG_ON(ir_index == -1);
memset (&irte, 0, sizeof(irte)); prepare_irte(&irte, cfg->vector, dest);
irte.present = 1;
irte.dst_mode = apic->irq_dest_mode;
irte.trigger_mode = 0; /* edge */
irte.dlvry_mode = apic->irq_delivery_mode;
irte.vector = cfg->vector;
irte.dest_id = IRTE_DEST(dest);
/* Set source-id of interrupt request */ /* Set source-id of interrupt request */
if (pdev) if (pdev)
......
...@@ -54,6 +54,9 @@ static int apicid_phys_pkg_id(int initial_apic_id, int index_msb) ...@@ -54,6 +54,9 @@ static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
*/ */
void __init default_setup_apic_routing(void) void __init default_setup_apic_routing(void)
{ {
enable_IR_x2apic();
#ifdef CONFIG_X86_X2APIC #ifdef CONFIG_X86_X2APIC
if (x2apic_mode if (x2apic_mode
#ifdef CONFIG_X86_UV #ifdef CONFIG_X86_UV
......
...@@ -1120,8 +1120,6 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) ...@@ -1120,8 +1120,6 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
} }
set_cpu_sibling_map(0); set_cpu_sibling_map(0);
enable_IR_x2apic();
default_setup_apic_routing();
if (smp_sanity_check(max_cpus) < 0) { if (smp_sanity_check(max_cpus) < 0) {
printk(KERN_INFO "SMP disabled\n"); printk(KERN_INFO "SMP disabled\n");
...@@ -1129,6 +1127,8 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) ...@@ -1129,6 +1127,8 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
goto out; goto out;
} }
default_setup_apic_routing();
preempt_disable(); preempt_disable();
if (read_apic_id() != boot_cpu_physical_apicid) { if (read_apic_id() != boot_cpu_physical_apicid) {
panic("Boot APIC ID in local APIC unexpected (%d vs %d)", panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
......
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