Commit 60c4bf29 authored by Felix Fietkau's avatar Felix Fietkau Committed by John W. Linville

ath9k_hw: remove defunct ad-hoc mode ATIM window handling code

The hardware does not have support for ATIM processing, and the driver
does not set up ah->atim_window anywhere. Additionally, the code can
clobber the timer used by P2P powersave.
Signed-off-by: default avatarFelix Fietkau <nbd@openwrt.org>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent c67ce339
...@@ -486,7 +486,6 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah) ...@@ -486,7 +486,6 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
ah->hw_version.magic = AR5416_MAGIC; ah->hw_version.magic = AR5416_MAGIC;
ah->hw_version.subvendorid = 0; ah->hw_version.subvendorid = 0;
ah->atim_window = 0;
ah->sta_id1_defaults = ah->sta_id1_defaults =
AR_STA_ID1_CRPT_MIC_ENABLE | AR_STA_ID1_CRPT_MIC_ENABLE |
AR_STA_ID1_MCAST_KSRCH; AR_STA_ID1_MCAST_KSRCH;
...@@ -2266,9 +2265,6 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) ...@@ -2266,9 +2265,6 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
case NL80211_IFTYPE_ADHOC: case NL80211_IFTYPE_ADHOC:
REG_SET_BIT(ah, AR_TXCFG, REG_SET_BIT(ah, AR_TXCFG,
AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
flags |= AR_NDP_TIMER_EN;
case NL80211_IFTYPE_MESH_POINT: case NL80211_IFTYPE_MESH_POINT:
case NL80211_IFTYPE_AP: case NL80211_IFTYPE_AP:
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
...@@ -2289,7 +2285,6 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) ...@@ -2289,7 +2285,6 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
......
...@@ -776,7 +776,6 @@ struct ath_hw { ...@@ -776,7 +776,6 @@ struct ath_hw {
u32 txurn_interrupt_mask; u32 txurn_interrupt_mask;
atomic_t intr_ref_cnt; atomic_t intr_ref_cnt;
bool chip_fullsleep; bool chip_fullsleep;
u32 atim_window;
u32 modes_index; u32 modes_index;
/* Calibration */ /* Calibration */
......
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