Commit 60dce695 authored by Biju Das's avatar Biju Das Committed by Simon Horman

ARM: dts: r8a7743: Add APMU node and second CPU core

Add DT nodes for the Advanced Power Management Unit (APMU) and the
second CPU core.  Use the enable-method to point out that the APMU
should be used for SMP support.
Signed-off-by: default avatarBiju Das <biju.das@bp.renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 02a5ab18
...@@ -30,6 +30,7 @@ aliases { ...@@ -30,6 +30,7 @@ aliases {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -41,6 +42,15 @@ cpu0: cpu@0 { ...@@ -41,6 +42,15 @@ cpu0: cpu@0 {
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
}; };
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
};
L2_CA15: cache-controller-0 { L2_CA15: cache-controller-0 {
compatible = "cache"; compatible = "cache";
cache-unified; cache-unified;
...@@ -57,6 +67,12 @@ soc { ...@@ -57,6 +67,12 @@ soc {
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
apmu@e6152000 {
compatible = "renesas,r8a7743-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
gic: interrupt-controller@f1001000 { gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
#interrupt-cells = <3>; #interrupt-cells = <3>;
......
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