drm/amdgpu/umsch: fix psp frontdoor loading

These changes are missed in rebase.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c

@@ -76,17 +76,6 @@ struct umsch_mm_test {
 	uint32_t		num_queues;
 };
 
-int umsch_mm_psp_update_sram(struct amdgpu_device *adev, u32 ucode_size)
-{
-	struct amdgpu_firmware_info ucode = {
-		.ucode_id = AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,
-		.mc_addr = adev->umsch_mm.cmd_buf_gpu_addr,
-		.ucode_size = ucode_size,
-	};
-
-	return psp_execute_ip_fw_load(&adev->psp, &ucode);
-}
-
 static int map_ring_data(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 			  struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,
 			  uint64_t addr, uint32_t size)
@@ -693,15 +682,17 @@ int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch)
 	return 0;
 }
 
-void* amdgpu_umsch_mm_add_cmd(struct amdgpu_umsch_mm *umsch,
-			      void* cmd_ptr, uint32_t reg_offset, uint32_t reg_data)
+int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch)
 {
-	uint32_t* ptr = (uint32_t *)cmd_ptr;
-
-	*ptr++ = (reg_offset << 2);
-	*ptr++ = reg_data;
+	struct amdgpu_device *adev = umsch->ring.adev;
+	struct amdgpu_firmware_info ucode = {
+		.ucode_id = AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,
+		.mc_addr = adev->umsch_mm.cmd_buf_gpu_addr,
+		.ucode_size = ((uintptr_t)adev->umsch_mm.cmd_buf_curr_ptr -
+			      (uintptr_t)adev->umsch_mm.cmd_buf_ptr),
+	};
 
-	return ptr;
+	return psp_execute_ip_fw_load(&adev->psp, &ucode);
 }
 
 static void umsch_mm_agdb_index_init(struct amdgpu_device *adev)
@@ -823,11 +814,9 @@ static int umsch_mm_hw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	int r;
 
-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
-		r = umsch_mm_load_microcode(&adev->umsch_mm);
-		if (r)
-			return r;
-	}
+	r = umsch_mm_load_microcode(&adev->umsch_mm);
+	if (r)
+		return r;
 
 	umsch_mm_ring_start(&adev->umsch_mm);
 

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h

@@ -150,6 +150,7 @@ struct amdgpu_umsch_mm {
 	struct amdgpu_bo		*cmd_buf_obj;
 	uint64_t			cmd_buf_gpu_addr;
 	uint32_t			*cmd_buf_ptr;
+	uint32_t			*cmd_buf_curr_ptr;
 
 	uint32_t			wb_index;
 	uint64_t			sch_ctx_gpu_addr;
@@ -167,19 +168,28 @@ struct amdgpu_umsch_mm {
 	struct mutex			mutex_hidden;
 };
 
-int umsch_mm_psp_update_sram(struct amdgpu_device *adev, u32 ucode_size);
-
 int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws);
 int amdgpu_umsch_mm_query_fence(struct amdgpu_umsch_mm *umsch);
 
 int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch);
 int amdgpu_umsch_mm_allocate_ucode_buffer(struct amdgpu_umsch_mm *umsch);
 int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch);
-void* amdgpu_umsch_mm_add_cmd(struct amdgpu_umsch_mm *umsch,
-			      void* cmd_ptr, uint32_t reg_offset, uint32_t reg_data);
+
+int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch);
 
 int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch);
 
+#define WREG32_SOC15_UMSCH(reg, value)								\
+	do {											\
+		uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg;	\
+		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {				\
+			*adev->umsch_mm.cmd_buf_curr_ptr++ = (reg_offset << 2);			\
+			*adev->umsch_mm.cmd_buf_curr_ptr++ = value;				\
+		} else	{									\
+			WREG32(reg_offset, value);						\
+		}										\
+	} while (0)
+
 #define umsch_mm_set_hw_resources(umsch) \
 	((umsch)->funcs->set_hw_resources ? (umsch)->funcs->set_hw_resources((umsch)) : 0)
 #define umsch_mm_add_queue(umsch, input) \

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

@@ -34,23 +34,10 @@
 #include "umsch_mm_4_0_api_def.h"
 #include "umsch_mm_v4_0.h"
 
-#define WREG32_SOC15_UMSCH(ptr, reg, value) \
-({	void *ret = ptr; 										\
-	do { 												\
-		uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; 		\
-		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)					\
-			ret = amdgpu_umsch_mm_add_cmd((&adev->umsch_mm), (ptr), (reg_offset), (value)); \
-		else											\
-			WREG32(reg_offset, value);							\
-	} while (0);											\
-	ret;												\
-})
-
 static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
 {
 	struct amdgpu_device *adev = umsch->ring.adev;
-	void* ptr = umsch->cmd_buf_ptr;
-	uint32_t data;
+	uint64_t data;
 	int r;
 
 	r = amdgpu_umsch_mm_allocate_ucode_buffer(umsch);
@@ -61,97 +48,95 @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
 	if (r)
 		goto err_free_ucode_bo;
 
+	umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
+
 	data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
 	data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0);
-	ptr = WREG32_SOC15_UMSCH(ptr, regUMSCH_MES_RESET_CTRL, data);
+	WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data);
 
 	data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);
 	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 1);
 	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 1);
 	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 0);
 	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 1);
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_CNTL, data);
+	WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);
 
 	data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_BASE_CNTL);
 	data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0);
 	data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, EXE_DISABLE, 0);
 	data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, CACHE_POLICY, 0);
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_BASE_CNTL, data);
+	WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_CNTL, data);
 
+	WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START,
+		lower_32_bits(adev->umsch_mm.irq_start_addr >> 2));
+	WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START_HI,
+		upper_32_bits(adev->umsch_mm.irq_start_addr >> 2));
 
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_INTR_ROUTINE_START,
-				 lower_32_bits(adev->umsch_mm.irq_start_addr >> 2));
+	WREG32_SOC15_UMSCH(regVCN_MES_PRGRM_CNTR_START,
+		lower_32_bits(adev->umsch_mm.uc_start_addr >> 2));
+	WREG32_SOC15_UMSCH(regVCN_MES_PRGRM_CNTR_START_HI,
+		upper_32_bits(adev->umsch_mm.uc_start_addr >> 2));
 
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_INTR_ROUTINE_START_HI,
-				 upper_32_bits(adev->umsch_mm.irq_start_addr >> 2));
-
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_PRGRM_CNTR_START,
-				 lower_32_bits(adev->umsch_mm.uc_start_addr >> 2));
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_PRGRM_CNTR_START_HI,
-				 upper_32_bits(adev->umsch_mm.uc_start_addr >> 2));
-
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_BASE_LO, 0);
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_BASE_HI, 0);
+	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_BASE_LO, 0);
+	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_BASE_HI, 0);
 
 	data = adev->umsch_mm.uc_start_addr + adev->umsch_mm.ucode_size - 1;
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data));
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_MASK_HI, upper_32_bits(data));
+	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data));
+	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_HI, upper_32_bits(data));
 
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_BASE_LO,
-				 lower_32_bits(adev->umsch_mm.ucode_fw_gpu_addr));
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_BASE_HI,
-				 upper_32_bits(adev->umsch_mm.ucode_fw_gpu_addr));
+	data = adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ?
+	       0 : adev->umsch_mm.ucode_fw_gpu_addr;
+	WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_LO, lower_32_bits(data));
+	WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_HI, upper_32_bits(data));
 
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_MIBOUND_LO, 0x1FFFFF);
+	WREG32_SOC15_UMSCH(regVCN_MES_MIBOUND_LO, 0x1FFFFF);
 
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_BASE0_LO,
-				 lower_32_bits(adev->umsch_mm.data_start_addr));
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_BASE0_HI,
-				 upper_32_bits(adev->umsch_mm.data_start_addr));
+	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_BASE0_LO,
+		lower_32_bits(adev->umsch_mm.data_start_addr));
+	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_BASE0_HI,
+		upper_32_bits(adev->umsch_mm.data_start_addr));
 
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_MASK0_LO,
-				 lower_32_bits(adev->umsch_mm.data_size - 1));
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_MASK0_HI,
-				 upper_32_bits(adev->umsch_mm.data_size - 1));
+	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_LO,
+		lower_32_bits(adev->umsch_mm.data_size - 1));
+	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_HI,
+		upper_32_bits(adev->umsch_mm.data_size - 1));
 
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_DC_BASE_LO,
-				 lower_32_bits(adev->umsch_mm.data_fw_gpu_addr));
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_DC_BASE_HI,
-				 upper_32_bits(adev->umsch_mm.data_fw_gpu_addr));
+	data = adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ?
+	       0 : adev->umsch_mm.data_fw_gpu_addr;
+	WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_LO, lower_32_bits(data));
+	WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_HI, upper_32_bits(data));
 
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_MDBOUND_LO, 0x3FFFF);
+	WREG32_SOC15_UMSCH(regVCN_MES_MDBOUND_LO, 0x3FFFF);
 
 	data = RREG32_SOC15(VCN, 0, regUVD_UMSCH_FORCE);
 	data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, IC_FORCE_GPUVM, 1);
 	data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, DC_FORCE_GPUVM, 1);
-	ptr = WREG32_SOC15_UMSCH(ptr, regUVD_UMSCH_FORCE, data);
+	WREG32_SOC15_UMSCH(regUVD_UMSCH_FORCE, data);
 
 	data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);
 	data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
 	data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_OP_CNTL, data);
+	WREG32_SOC15_UMSCH(regVCN_MES_IC_OP_CNTL, data);
 
 	data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);
 	data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_OP_CNTL, data);
+	WREG32_SOC15_UMSCH(regVCN_MES_IC_OP_CNTL, data);
 
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP0_LO, 0);
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP0_HI, 0);
+	WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, 0);
+	WREG32_SOC15_UMSCH(regVCN_MES_GP0_HI, 0);
 
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP1_LO, 0);
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP1_HI, 0);
+	WREG32_SOC15_UMSCH(regVCN_MES_GP1_LO, 0);
+	WREG32_SOC15_UMSCH(regVCN_MES_GP1_HI, 0);
 
 	data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);
 	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 0);
 	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 0);
 	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 0);
 	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 1);
-	ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_CNTL, data);
+	WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);
 
-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-		umsch_mm_psp_update_sram(adev,
-					 (u32)((uintptr_t)ptr - (uintptr_t)umsch->cmd_buf_ptr));
-	}
+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
+		amdgpu_umsch_mm_psp_execute_cmd_buf(umsch);
 
 	r = SOC15_WAIT_ON_RREG(VCN, 0, regVCN_MES_MSTATUS_LO, 0xAAAAAAAA, 0xFFFFFFFF);
 	if (r) {