Commit 619ba451 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab

docs: bus-devices: ti-gpmc.rst: convert it to ReST

In order to be able to add this file to a book, it needs
first to be converted to ReST and renamed.

While this is not part of any book, mark it as :orphan:, in order
to avoid build warnings.
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 675aaf05
GPMC (General Purpose Memory Controller): :orphan:
=========================================
========================================
GPMC (General Purpose Memory Controller)
========================================
GPMC is an unified memory controller dedicated to interfacing external GPMC is an unified memory controller dedicated to interfacing external
memory devices like memory devices like
* Asynchronous SRAM like memories and application specific integrated * Asynchronous SRAM like memories and application specific integrated
circuit devices. circuit devices.
* Asynchronous, synchronous, and page mode burst NOR flash devices * Asynchronous, synchronous, and page mode burst NOR flash devices
...@@ -48,75 +52,128 @@ most of the datasheets & hardware (to be exact none of those supported ...@@ -48,75 +52,128 @@ most of the datasheets & hardware (to be exact none of those supported
in mainline having custom timing routine) and by simulation. in mainline having custom timing routine) and by simulation.
gpmc timing dependency on peripheral timings: gpmc timing dependency on peripheral timings:
[<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...] [<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...]
1. common 1. common
cs_on: t_ceasu
adv_on: t_avdasu, t_ceavd cs_on:
t_ceasu
adv_on:
t_avdasu, t_ceavd
2. sync common 2. sync common
sync_clk: clk
page_burst_access: t_bacc sync_clk:
clk_activation: t_ces, t_avds clk
page_burst_access:
t_bacc
clk_activation:
t_ces, t_avds
3. read async muxed 3. read async muxed
adv_rd_off: t_avdp_r
oe_on: t_oeasu, t_aavdh adv_rd_off:
access: t_iaa, t_oe, t_ce, t_aa t_avdp_r
rd_cycle: t_rd_cycle, t_cez_r, t_oez oe_on:
t_oeasu, t_aavdh
access:
t_iaa, t_oe, t_ce, t_aa
rd_cycle:
t_rd_cycle, t_cez_r, t_oez
4. read async non-muxed 4. read async non-muxed
adv_rd_off: t_avdp_r
oe_on: t_oeasu adv_rd_off:
access: t_iaa, t_oe, t_ce, t_aa t_avdp_r
rd_cycle: t_rd_cycle, t_cez_r, t_oez oe_on:
t_oeasu
access:
t_iaa, t_oe, t_ce, t_aa
rd_cycle:
t_rd_cycle, t_cez_r, t_oez
5. read sync muxed 5. read sync muxed
adv_rd_off: t_avdp_r, t_avdh
oe_on: t_oeasu, t_ach, cyc_aavdh_oe adv_rd_off:
access: t_iaa, cyc_iaa, cyc_oe t_avdp_r, t_avdh
rd_cycle: t_cez_r, t_oez, t_ce_rdyz oe_on:
t_oeasu, t_ach, cyc_aavdh_oe
access:
t_iaa, cyc_iaa, cyc_oe
rd_cycle:
t_cez_r, t_oez, t_ce_rdyz
6. read sync non-muxed 6. read sync non-muxed
adv_rd_off: t_avdp_r
oe_on: t_oeasu adv_rd_off:
access: t_iaa, cyc_iaa, cyc_oe t_avdp_r
rd_cycle: t_cez_r, t_oez, t_ce_rdyz oe_on:
t_oeasu
access:
t_iaa, cyc_iaa, cyc_oe
rd_cycle:
t_cez_r, t_oez, t_ce_rdyz
7. write async muxed 7. write async muxed
adv_wr_off: t_avdp_w
we_on, wr_data_mux_bus: t_weasu, t_aavdh, cyc_aavhd_we adv_wr_off:
we_off: t_wpl t_avdp_w
cs_wr_off: t_wph we_on, wr_data_mux_bus:
wr_cycle: t_cez_w, t_wr_cycle t_weasu, t_aavdh, cyc_aavhd_we
we_off:
t_wpl
cs_wr_off:
t_wph
wr_cycle:
t_cez_w, t_wr_cycle
8. write async non-muxed 8. write async non-muxed
adv_wr_off: t_avdp_w
we_on, wr_data_mux_bus: t_weasu adv_wr_off:
we_off: t_wpl t_avdp_w
cs_wr_off: t_wph we_on, wr_data_mux_bus:
wr_cycle: t_cez_w, t_wr_cycle t_weasu
we_off:
t_wpl
cs_wr_off:
t_wph
wr_cycle:
t_cez_w, t_wr_cycle
9. write sync muxed 9. write sync muxed
adv_wr_off: t_avdp_w, t_avdh
we_on, wr_data_mux_bus: t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we adv_wr_off:
we_off: t_wpl, cyc_wpl t_avdp_w, t_avdh
cs_wr_off: t_wph we_on, wr_data_mux_bus:
wr_cycle: t_cez_w, t_ce_rdyz t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we
we_off:
t_wpl, cyc_wpl
cs_wr_off:
t_wph
wr_cycle:
t_cez_w, t_ce_rdyz
10. write sync non-muxed 10. write sync non-muxed
adv_wr_off: t_avdp_w
we_on, wr_data_mux_bus: t_weasu, t_rdyo adv_wr_off:
we_off: t_wpl, cyc_wpl t_avdp_w
cs_wr_off: t_wph we_on, wr_data_mux_bus:
wr_cycle: t_cez_w, t_ce_rdyz t_weasu, t_rdyo
we_off:
t_wpl, cyc_wpl
Note: Many of gpmc timings are dependent on other gpmc timings (a few cs_wr_off:
gpmc timings purely dependent on other gpmc timings, a reason that t_wph
some of the gpmc timings are missing above), and it will result in wr_cycle:
indirect dependency of peripheral timings to gpmc timings other than t_cez_w, t_ce_rdyz
mentioned above, refer timing routine for more details. To know what
these peripheral timings correspond to, please see explanations in
struct gpmc_device_timings definition. And for gpmc timings refer Note:
IP details (link above). Many of gpmc timings are dependent on other gpmc timings (a few
gpmc timings purely dependent on other gpmc timings, a reason that
some of the gpmc timings are missing above), and it will result in
indirect dependency of peripheral timings to gpmc timings other than
mentioned above, refer timing routine for more details. To know what
these peripheral timings correspond to, please see explanations in
struct gpmc_device_timings definition. And for gpmc timings refer
IP details (link above).
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