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Commit 61b7f892 authored by Arnd Bergmann's avatar Arnd Bergmann
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ARM: s3c: remove all s3c24xx support 

The platform was deprecated in commit 6a5e69c7 ("ARM: s3c: mark
as deprecated and schedule removal") and can be removed. This includes
all files that are exclusively for s3c24xx and not shared with s3c64xx,
as well as the glue logic in Kconfig and the maintainer file entries.

Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Christer Weinigel <christer@weinigel.se>
Cc: Guillaume GOURAT <guillaume.gourat@nexvision.tv>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Simtec Linux Team <linux@simtec.co.uk>
Cc: openmoko-kernel@lists.openmoko.org
Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 1027b4df
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Documentation/arm/index.rst
View file @ 61b7f892
......@@ -64,7 +64,6 @@ SoC-specific documents
sunxi
samsung/index
samsung-s3c24xx/index
sunxi/clocks
......
Documentation/arm/samsung-s3c24xx/cpufreq.rst deleted 100644 → 0
View file @ 1027b4df
.. SPDX-License-Identifier: GPL-2.0-only
=======================
S3C24XX CPUfreq support
=======================
Introduction
------------
The S3C24XX series support a number of power saving systems, such as
the ability to change the core, memory and peripheral operating
frequencies. The core control is exported via the CPUFreq driver
which has a number of different manual or automatic controls over the
rate the core is running at.
There are two forms of the driver depending on the specific CPU and
how the clocks are arranged. The first implementation used as single
PLL to feed the ARM, memory and peripherals via a series of dividers
and muxes and this is the implementation that is documented here. A
newer version where there is a separate PLL and clock divider for the
ARM core is available as a separate driver.
Layout
------
The code core manages the CPU specific drivers, any data that they
need to register and the interface to the generic drivers/cpufreq
system. Each CPU registers a driver to control the PLL, clock dividers
and anything else associated with it. Any board that wants to use this
framework needs to supply at least basic details of what is required.
The core registers with drivers/cpufreq at init time if all the data
necessary has been supplied.
CPU support
-----------
The support for each CPU depends on the facilities provided by the
SoC and the driver as each device has different PLL and clock chains
associated with it.
Slow Mode
---------
The SLOW mode where the PLL is turned off altogether and the
system is fed by the external crystal input is currently not
supported.
sysfs
-----
The core code exports extra information via sysfs in the directory
devices/system/cpu/cpu0/arch-freq.
Board Support
-------------
Each board that wants to use the cpufreq code must register some basic
information with the core driver to provide information about what the
board requires and any restrictions being placed on it.
The board needs to supply information about whether it needs the IO bank
timings changing, any maximum frequency limits and information about the
SDRAM refresh rate.
Document Author
---------------
Ben Dooks, Copyright 2009 Simtec Electronics
Documentation/arm/samsung-s3c24xx/eb2410itx.rst deleted 100644 → 0
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===================================
Simtec Electronics EB2410ITX (BAST)
===================================
http://www.simtec.co.uk/products/EB2410ITX/
Introduction
------------
The EB2410ITX is a S3C2410 based development board with a variety of
peripherals and expansion connectors. This board is also known by
the shortened name of Bast.
Configuration
-------------
To set the default configuration, use `make bast_defconfig` which
supports the commonly used features of this board.
Support
-------
Official support information can be found on the Simtec Electronics
website, at the product page http://www.simtec.co.uk/products/EB2410ITX/
Useful links:
- Resources Page http://www.simtec.co.uk/products/EB2410ITX/resources.html
- Board FAQ at http://www.simtec.co.uk/products/EB2410ITX/faq.html
- Bootloader info http://www.simtec.co.uk/products/SWABLE/resources.html
and FAQ http://www.simtec.co.uk/products/SWABLE/faq.html
MTD
---
The NAND and NOR support has been merged from the linux-mtd project.
Any problems, see http://www.linux-mtd.infradead.org/ for more
information or up-to-date versions of linux-mtd.
IDE
---
Both onboard IDE ports are supported, however there is no support for
changing speed of devices, PIO Mode 4 capable drives should be used.
Maintainers
-----------
This board is maintained by Simtec Electronics.
Copyright 2004 Ben Dooks, Simtec Electronics
Documentation/arm/samsung-s3c24xx/gpio.rst deleted 100644 → 0
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====================
S3C24XX GPIO Control
====================
Introduction
------------
The s3c2410 kernel provides an interface to configure and
manipulate the state of the GPIO pins, and find out other
information about them.
There are a number of conditions attached to the configuration
of the s3c2410 GPIO system, please read the Samsung provided
data-sheet/users manual to find out the complete list.
See Documentation/arm/samsung/gpio.rst for the core implementation.
GPIOLIB
-------
With the event of the GPIOLIB in drivers/gpio, support for some
of the GPIO functions such as reading and writing a pin will
be removed in favour of this common access method.
Once all the extant drivers have been converted, the functions
listed below will be removed (they may be marked as __deprecated
in the near future).
The following functions now either have a `s3c_` specific variant
or are merged into gpiolib. See the definitions in
arch/arm/mach-s3c/gpio-cfg.h:
- s3c2410_gpio_setpin() gpio_set_value() or gpio_direction_output()
- s3c2410_gpio_getpin() gpio_get_value() or gpio_direction_input()
- s3c2410_gpio_getirq() gpio_to_irq()
- s3c2410_gpio_cfgpin() s3c_gpio_cfgpin()
- s3c2410_gpio_getcfg() s3c_gpio_getcfg()
- s3c2410_gpio_pullup() s3c_gpio_setpull()
GPIOLIB conversion
------------------
If you need to convert your board or driver to use gpiolib from the phased
out s3c2410 API, then here are some notes on the process.
1) If your board is exclusively using an GPIO, say to control peripheral
power, then it will require to claim the gpio with gpio_request() before
it can use it.
It is recommended to check the return value, with at least WARN_ON()
during initialisation.
2) The s3c2410_gpio_cfgpin() can be directly replaced with s3c_gpio_cfgpin()
as they have the same arguments, and can either take the pin specific
values, or the more generic special-function-number arguments.
3) s3c2410_gpio_pullup() changes have the problem that while the
s3c2410_gpio_pullup(x, 1) can be easily translated to the
s3c_gpio_setpull(x, S3C_GPIO_PULL_NONE), the s3c2410_gpio_pullup(x, 0)
are not so easy.
The s3c2410_gpio_pullup(x, 0) case enables the pull-up (or in the case
of some of the devices, a pull-down) and as such the new API distinguishes
between the UP and DOWN case. There is currently no 'just turn on' setting
which may be required if this becomes a problem.
4) s3c2410_gpio_setpin() can be replaced by gpio_set_value(), the old call
does not implicitly configure the relevant gpio to output. The gpio
direction should be changed before using gpio_set_value().
5) s3c2410_gpio_getpin() is replaceable by gpio_get_value() if the pin
has been set to input. It is currently unknown what the behaviour is
when using gpio_get_value() on an output pin (s3c2410_gpio_getpin
would return the value the pin is supposed to be outputting).
6) s3c2410_gpio_getirq() should be directly replaceable with the
gpio_to_irq() call.
The s3c2410_gpio and `gpio_` calls have always operated on the same gpio
numberspace, so there is no problem with converting the gpio numbering
between the calls.
Headers
-------
See arch/arm/mach-s3c/regs-gpio-s3c24xx.h for the list
of GPIO pins, and the configuration values for them. This
is included by using #include <mach/regs-gpio.h>
PIN Numbers
-----------
Each pin has an unique number associated with it in regs-gpio.h,
e.g. S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
the GPIO functions which pin is to be used.
With the conversion to gpiolib, there is no longer a direct conversion
from gpio pin number to register base address as in earlier kernels. This
is due to the number space required for newer SoCs where the later
GPIOs are not contiguous.
Configuring a pin
-----------------
The following function allows the configuration of a given pin to
be changed.
void s3c_gpio_cfgpin(unsigned int pin, unsigned int function);
e.g.:
s3c_gpio_cfgpin(S3C2410_GPA(0), S3C_GPIO_SFN(1));
s3c_gpio_cfgpin(S3C2410_GPE(8), S3C_GPIO_SFN(2));
which would turn GPA(0) into the lowest Address line A0, and set
GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line.
Reading the current configuration
---------------------------------
The current configuration of a pin can be read by using standard
gpiolib function:
s3c_gpio_getcfg(unsigned int pin);
The return value will be from the same set of values which can be
passed to s3c_gpio_cfgpin().
Configuring a pull-up resistor
------------------------------
A large proportion of the GPIO pins on the S3C2410 can have weak
pull-up resistors enabled. This can be configured by the following
function:
void s3c_gpio_setpull(unsigned int pin, unsigned int to);
Where the to value is S3C_GPIO_PULL_NONE to set the pull-up off,
and S3C_GPIO_PULL_UP to enable the specified pull-up. Any other
values are currently undefined.
Getting and setting the state of a PIN
--------------------------------------
These calls are now implemented by the relevant gpiolib calls, convert
your board or driver to use gpiolib.
Getting the IRQ number associated with a PIN
--------------------------------------------
A standard gpiolib function can map the given pin number to an IRQ
number to pass to the IRQ system.
int gpio_to_irq(unsigned int pin);
Note, not all pins have an IRQ.
Author
-------
Ben Dooks, 03 October 2004
Copyright 2004 Ben Dooks, Simtec Electronics
Documentation/arm/samsung-s3c24xx/h1940.rst deleted 100644 → 0
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=============
HP IPAQ H1940
=============
http://www.handhelds.org/projects/h1940.html
Introduction
------------
The HP H1940 is a S3C2410 based handheld device, with
bluetooth connectivity.
Support
-------
A variety of information is available
handhelds.org project page:
http://www.handhelds.org/projects/h1940.html
handhelds.org wiki page:
http://handhelds.org/moin/moin.cgi/HpIpaqH1940
Herbert Pötzl pages:
http://vserver.13thfloor.at/H1940/
Maintainers
-----------
This project is being maintained and developed by a variety
of people, including Ben Dooks, Arnaud Patard, and Herbert Pötzl.
Thanks to the many others who have also provided support.
(c) 2005 Ben Dooks
Documentation/arm/samsung-s3c24xx/index.rst deleted 100644 → 0
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.. SPDX-License-Identifier: GPL-2.0
==========================
Samsung S3C24XX SoC Family
==========================
.. toctree::
:maxdepth: 1
h1940
gpio
cpufreq
suspend
usb-host
s3c2412
eb2410itx
nand
smdk2440
s3c2413
overview
Documentation/arm/samsung-s3c24xx/nand.rst deleted 100644 → 0
View file @ 1027b4df
====================
S3C24XX NAND Support
====================
Introduction
------------
Small Page NAND
---------------
The driver uses a 512 byte (1 page) ECC code for this setup. The
ECC code is not directly compatible with the default kernel ECC
code, so the driver enforces its own OOB layout and ECC parameters
Large Page NAND
---------------
The driver is capable of handling NAND flash with a 2KiB page
size, with support for hardware ECC generation and correction.
Unlike the 512byte page mode, the driver generates ECC data for
each 256 byte block in an 2KiB page. This means that more than
one error in a page can be rectified. It also means that the
OOB layout remains the default kernel layout for these flashes.
Document Author
---------------
Ben Dooks, Copyright 2007 Simtec Electronics
Documentation/arm/samsung-s3c24xx/overview.rst deleted 100644 → 0
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==========================
S3C24XX ARM Linux Overview
==========================
Introduction
------------
The Samsung S3C24XX range of ARM9 System-on-Chip CPUs are supported
by the 's3c2410' architecture of ARM Linux. Currently the S3C2410,
S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 and S3C2450 devices
are supported.
Support for the S3C2400 and S3C24A0 series was never completed and the
corresponding code has been removed after a while. If someone wishes to
revive this effort, partial support can be retrieved from earlier Linux
versions.
The S3C2416 and S3C2450 devices are very similar and S3C2450 support is
included under the arch/arm/mach-s3c directory. Note, while core
support for these SoCs is in, work on some of the extra peripherals
and extra interrupts is still ongoing.
Configuration
-------------
A generic S3C2410 configuration is provided, and can be used as the
default by `make s3c2410_defconfig`. This configuration has support
for all the machines, and the commonly used features on them.
Certain machines may have their own default configurations as well,
please check the machine specific documentation.
Layout
------
The core support files, register, kernel and paltform data are located in the
platform code contained in arch/arm/mach-s3c with headers in
arch/arm/mach-s3c/include
arch/arm/mach-s3c:
Files in here are either common to all the s3c24xx family,
or are common to only some of them with names to indicate this
status. The files that are not common to all are generally named
with the initial cpu they support in the series to ensure a short
name without any possibility of confusion with newer devices.
As an example, initially s3c244x would cover s3c2440 and s3c2442, but
with the s3c2443 which does not share many of the same drivers in
this directory, the name becomes invalid. We stick to s3c2440-<x>
to indicate a driver that is s3c2440 and s3c2442 compatible.
This does mean that to find the status of any given SoC, a number
of directories may need to be searched.
Machines
--------
The currently supported machines are as follows:
Simtec Electronics EB2410ITX (BAST)
A general purpose development board, see EB2410ITX.txt for further
details
Simtec Electronics IM2440D20 (Osiris)
CPU Module from Simtec Electronics, with a S3C2440A CPU, nand flash
and a PCMCIA controller.
Samsung SMDK2410
Samsung's own development board, geared for PDA work.
Samsung/Aiji SMDK2412
The S3C2412 version of the SMDK2440.
Samsung/Aiji SMDK2413
The S3C2412 version of the SMDK2440.
Samsung/Meritech SMDK2440
The S3C2440 compatible version of the SMDK2440, which has the
option of an S3C2440 or S3C2442 CPU module.
Thorcom VR1000
Custom embedded board
HP IPAQ 1940
Handheld (IPAQ), available in several varieties
HP iPAQ rx3715
S3C2440 based IPAQ, with a number of variations depending on
features shipped.
Acer N30
A S3C2410 based PDA from Acer. There is a Wiki page at
http://handhelds.org/moin/moin.cgi/AcerN30Documentation .
AML M5900
American Microsystems' M5900
Nex Vision Nexcoder
Nex Vision Otom
Two machines by Nex Vision
Adding New Machines
-------------------
The architecture has been designed to support as many machines as can
be configured for it in one kernel build, and any future additions
should keep this in mind before altering items outside of their own
machine files.
Machine definitions should be kept in arch/arm/mach-s3c,
and there are a number of examples that can be looked at.
Read the kernel patch submission policies as well as the
Documentation/arm directory before submitting patches. The
ARM kernel series is managed by Russell King, and has a patch system
located at http://www.arm.linux.org.uk/developer/patches/
as well as mailing lists that can be found from the same site.
As a courtesy, please notify <ben-linux@fluff.org> of any new
machines or other modifications.
Any large scale modifications, or new drivers should be discussed
on the ARM kernel mailing list (linux-arm-kernel) before being
attempted. See http://www.arm.linux.org.uk/mailinglists/ for the
mailing list information.
I2C
---
The hardware I2C core in the CPU is supported in single master
mode, and can be configured via platform data.
RTC
---
Support for the onboard RTC unit, including alarm function.
This has recently been upgraded to use the new RTC core,
and the module has been renamed to rtc-s3c to fit in with
the new rtc naming scheme.
Watchdog
--------
The onchip watchdog is available via the standard watchdog
interface.
NAND
----
The current kernels now have support for the s3c2410 NAND
controller. If there are any problems the latest linux-mtd
code can be found from http://www.linux-mtd.infradead.org/
For more information see Documentation/arm/samsung-s3c24xx/nand.rst
SD/MMC
------
The SD/MMC hardware pre S3C2443 is supported in the current
kernel, the driver is drivers/mmc/host/s3cmci.c and supports
1 and 4 bit SD or MMC cards.
The SDIO behaviour of this driver has not been fully tested. There is no
current support for hardware SDIO interrupts.
Serial
------
The s3c2410 serial driver provides support for the internal
serial ports. These devices appear as /dev/ttySAC0 through 3.
To create device nodes for these, use the following commands
mknod ttySAC0 c 204 64
mknod ttySAC1 c 204 65
mknod ttySAC2 c 204 66
GPIO
----
The core contains support for manipulating the GPIO, see the
documentation in GPIO.txt in the same directory as this file.
Newer kernels carry GPIOLIB, and support is being moved towards
this with some of the older support in line to be removed.
As of v2.6.34, the move towards using gpiolib support is almost
complete, and very little of the old calls are left.
See Documentation/arm/samsung-s3c24xx/gpio.rst for the S3C24XX specific
support and Documentation/arm/samsung/gpio.rst for the core Samsung
implementation.
Clock Management
----------------
The core provides the interface defined in the header file
include/asm-arm/hardware/clock.h, to allow control over the
various clock units
Suspend to RAM
--------------
For boards that provide support for suspend to RAM, the
system can be placed into low power suspend.
See Suspend.txt for more information.
SPI
---
SPI drivers are available for both the in-built hardware
(although there is no DMA support yet) and a generic
GPIO based solution.
LEDs
----
There is support for GPIO based LEDs via a platform driver
in the LED subsystem.
Platform Data
-------------
Whenever a device has platform specific data that is specified
on a per-machine basis, care should be taken to ensure the
following:
1) that default data is not left in the device to confuse the
driver if a machine does not set it at startup
2) the data should (if possible) be marked as __initdata,
to ensure that the data is thrown away if the machine is
not the one currently in use.
The best way of doing this is to make a function that
kmalloc()s an area of memory, and copies the __initdata
and then sets the relevant device's platform data. Making
the function `__init` takes care of ensuring it is discarded
with the rest of the initialisation code::
static __init void s3c24xx_xxx_set_platdata(struct xxx_data *pd)
{
struct s3c2410_xxx_mach_info *npd;
npd = kmalloc(sizeof(struct s3c2410_xxx_mach_info), GFP_KERNEL);
if (npd) {
memcpy(npd, pd, sizeof(struct s3c2410_xxx_mach_info));
s3c_device_xxx.dev.platform_data = npd;
} else {
printk(KERN_ERR "no memory for xxx platform data\n");
}
}
Note, since the code is marked as __init, it should not be
exported outside arch/arm/mach-s3c/, or exported to
modules via EXPORT_SYMBOL() and related functions.
Port Contributors
-----------------
Ben Dooks (BJD)
Vincent Sanders
Herbert Potzl
Arnaud Patard (RTP)
Roc Wu
Klaus Fetscher
Dimitry Andric
Shannon Holland
Guillaume Gourat (NexVision)
Christer Weinigel (wingel) (Acer N30)
Lucas Correia Villa Real (S3C2400 port)
Document Author
---------------
Ben Dooks, Copyright 2004-2006 Simtec Electronics
Documentation/arm/samsung-s3c24xx/s3c2412.rst deleted 100644 → 0
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==========================
S3C2412 ARM Linux Overview
==========================
Introduction
------------
The S3C2412 is part of the S3C24XX range of ARM9 System-on-Chip CPUs
from Samsung. This part has an ARM926-EJS core, capable of running up
to 266MHz (see data-sheet for more information)
Clock
-----
The core clock code provides a set of clocks to the drivers, and allows
for source selection and a number of other features.
Power
-----
No support for suspend/resume to RAM in the current system.
DMA
---
No current support for DMA.
GPIO
----
There is support for setting the GPIO to input/output/special function
and reading or writing to them.
UART
----
The UART hardware is similar to the S3C2440, and is supported by the
s3c2410 driver in the drivers/serial directory.
NAND
----
The NAND hardware is similar to the S3C2440, and is supported by the
s3c2410 driver in the drivers/mtd/nand/raw directory.
USB Host
--------
The USB hardware is similar to the S3C2410, with extended clock source
control. The OHCI portion is supported by the ohci-s3c2410 driver, and
the clock control selection is supported by the core clock code.
USB Device
----------
No current support in the kernel
IRQs
----
All the standard, and external interrupt sources are supported. The
extra sub-sources are not yet supported.
RTC
---
The RTC hardware is similar to the S3C2410, and is supported by the
s3c2410-rtc driver.
Watchdog
--------
The watchdog hardware is the same as the S3C2410, and is supported by
the s3c2410_wdt driver.
MMC/SD/SDIO
-----------
No current support for the MMC/SD/SDIO block.
IIC
---
The IIC hardware is the same as the S3C2410, and is supported by the
i2c-s3c24xx driver.
IIS
---
No current support for the IIS interface.
SPI
---
No current support for the SPI interfaces.
ATA
---
No current support for the on-board ATA block.
Document Author
---------------
Ben Dooks, Copyright 2006 Simtec Electronics
Documentation/arm/samsung-s3c24xx/s3c2413.rst deleted 100644 → 0
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==========================
S3C2413 ARM Linux Overview
==========================
Introduction
------------
The S3C2413 is an extended version of the S3C2412, with an camera
interface and mobile DDR memory support. See the S3C2412 support
documentation for more information.
Camera Interface
----------------
This block is currently not supported.
Document Author
---------------
Ben Dooks, Copyright 2006 Simtec Electronics
Documentation/arm/samsung-s3c24xx/smdk2440.rst deleted 100644 → 0
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=========================
Samsung/Meritech SMDK2440
=========================
Introduction
------------
The SMDK2440 is a two part evaluation board for the Samsung S3C2440
processor. It includes support for LCD, SmartMedia, Audio, SD and
10MBit Ethernet, and expansion headers for various signals, including
the camera and unused GPIO.
Configuration
-------------
To set the default configuration, use `make smdk2440_defconfig` which
will configure the common features of this board, or use
`make s3c2410_config` to include support for all s3c2410/s3c2440 machines
Support
-------
Ben Dooks' SMDK2440 site at http://www.fluff.org/ben/smdk2440/ which
includes linux based USB download tools.
Some of the h1940 patches that can be found from the H1940 project
site at http://www.handhelds.org/projects/h1940.html can also be
applied to this board.
Peripherals
-----------
There is no current support for any of the extra peripherals on the
base-board itself.
MTD
---
The NAND flash should be supported by the in kernel MTD NAND support,
NOR flash will be added later.
Maintainers
-----------
This board is being maintained by Ben Dooks, for more info, see
http://www.fluff.org/ben/smdk2440/
Many thanks to Dimitry Andric of TomTom for the loan of the SMDK2440,
and to Simtec Electronics for allowing me time to work on this.
(c) 2004 Ben Dooks
Documentation/arm/samsung-s3c24xx/suspend.rst deleted 100644 → 0
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=======================
S3C24XX Suspend Support
=======================
Introduction
------------
The S3C24XX supports a low-power suspend mode, where the SDRAM is kept
in Self-Refresh mode, and all but the essential peripheral blocks are
powered down. For more information on how this works, please look
at the relevant CPU datasheet from Samsung.
Requirements
------------
1) A bootloader that can support the necessary resume operation
2) Support for at least 1 source for resume
3) CONFIG_PM enabled in the kernel
4) Any peripherals that are going to be powered down at the same
time require suspend/resume support.
Resuming
--------
The S3C2410 user manual defines the process of sending the CPU to
sleep and how it resumes. The default behaviour of the Linux code
is to set the GSTATUS3 register to the physical address of the
code to resume Linux operation.
GSTATUS4 is currently left alone by the sleep code, and is free to
use for any other purposes (for example, the EB2410ITX uses this to
save memory configuration in).
Machine Support
---------------
The machine specific functions must call the s3c_pm_init() function
to say that its bootloader is capable of resuming. This can be as
simple as adding the following to the machine's definition:
INITMACHINE(s3c_pm_init)
A board can do its own setup before calling s3c_pm_init, if it
needs to setup anything else for power management support.
There is currently no support for over-riding the default method of
saving the resume address, if your board requires it, then contact
the maintainer and discuss what is required.
Note, the original method of adding an late_initcall() is wrong,
and will end up initialising all compiled machines' pm init!
The following is an example of code used for testing wakeup from
an falling edge on IRQ_EINT0::
static irqreturn_t button_irq(int irq, void *pw)
{
return IRQ_HANDLED;
}
statuc void __init machine_init(void)
{
...
request_irq(IRQ_EINT0, button_irq, IRQF_TRIGGER_FALLING,
"button-irq-eint0", NULL);
enable_irq_wake(IRQ_EINT0);
s3c_pm_init();
}
Debugging
---------
There are several important things to remember when using PM suspend:
1) The uart drivers will disable the clocks to the UART blocks when
suspending, which means that use of printascii() or similar direct
access to the UARTs will cause the debug to stop.
2) While the pm code itself will attempt to re-enable the UART clocks,
care should be taken that any external clock sources that the UARTs
rely on are still enabled at that point.
3) If any debugging is placed in the resume path, then it must have the
relevant clocks and peripherals setup before use (ie, bootloader).
For example, if you transmit a character from the UART, the baud
rate and uart controls must be setup beforehand.
Configuration
-------------
The S3C2410 specific configuration in `System Type` defines various
aspects of how the S3C2410 suspend and resume support is configured
`S3C2410 PM Suspend debug`
This option prints messages to the serial console before and after
the actual suspend, giving detailed information on what is
happening
`S3C2410 PM Suspend Memory CRC`
Allows the entire memory to be checksummed before and after the
suspend to see if there has been any corruption of the contents.
Note, the time to calculate the CRC is dependent on the CPU speed
and the size of memory. For an 64Mbyte RAM area on an 200MHz
S3C2410, this can take approximately 4 seconds to complete.
This support requires the CRC32 function to be enabled.
`S3C2410 PM Suspend CRC Chunksize (KiB)`
Defines the size of memory each CRC chunk covers. A smaller value
will mean that the CRC data block will take more memory, but will
identify any faults with better precision
Document Author
---------------
Ben Dooks, Copyright 2004 Simtec Electronics
Documentation/arm/samsung-s3c24xx/usb-host.rst deleted 100644 → 0
View file @ 1027b4df
========================
S3C24XX USB Host support
========================
Introduction
------------
This document details the S3C2410/S3C2440 in-built OHCI USB host support.
Configuration
-------------
Enable at least the following kernel options:
menuconfig::
Device Drivers --->
USB support --->
<*> Support for Host-side USB
<*> OHCI HCD support
.config:
- CONFIG_USB
- CONFIG_USB_OHCI_HCD
Once these options are configured, the standard set of USB device
drivers can be configured and used.
Board Support
-------------
The driver attaches to a platform device, which will need to be
added by the board specific support file in arch/arm/mach-s3c,
such as mach-bast.c or mach-smdk2410.c
The platform device's platform_data field is only needed if the
board implements extra power control or over-current monitoring.
The OHCI driver does not ensure the state of the S3C2410's MISCCTRL
register, so if both ports are to be used for the host, then it is
the board support file's responsibility to ensure that the second
port is configured to be connected to the OHCI core.
Platform Data
-------------
See include/linux/platform_data/usb-ohci-s3c2410.h for the
descriptions of the platform device data. An implementation
can be found in arch/arm/mach-s3c/simtec-usb.c .
The `struct s3c2410_hcd_info` contains a pair of functions
that get called to enable over-current detection, and to
control the port power status.
The ports are numbered 0 and 1.
power_control:
Called to enable or disable the power on the port.
enable_oc:
Called to enable or disable the over-current monitoring.
This should claim or release the resources being used to
check the power condition on the port, such as an IRQ.
report_oc:
The OHCI driver fills this field in for the over-current code
to call when there is a change to the over-current state on
an port. The ports argument is a bitmask of 1 bit per port,
with bit X being 1 for an over-current on port X.
The function s3c2410_usb_report_oc() has been provided to
ensure this is called correctly.
port[x]:
This is struct describes each port, 0 or 1. The platform driver
should set the flags field of each port to S3C_HCDFLG_USED if
the port is enabled.
Document Author
---------------
Ben Dooks, Copyright 2005 Simtec Electronics
Documentation/arm/samsung/gpio.rst
View file @ 61b7f892
......@@ -9,14 +9,6 @@ This outlines the Samsung GPIO implementation and the architecture
specific calls provided alongside the drivers/gpio core.
S3C24XX (Legacy)
----------------
See Documentation/arm/samsung-s3c24xx/gpio.rst for more information
about these devices. Their implementation has been brought into line
with the core samsung implementation described in this document.
GPIOLIB integration
-------------------
......
Documentation/arm/samsung/overview.rst
View file @ 61b7f892
......@@ -12,21 +12,10 @@ Introduction
The currently supported SoCs are:
- S3C24XX: See Documentation/arm/samsung-s3c24xx/overview.rst for full list
- S3C64XX: S3C6400 and S3C6410
- S5PC110 / S5PV210
S3C24XX Systems
---------------
There is still documentation in Documnetation/arm/Samsung-S3C24XX/ which
deals with the architecture and drivers specific to these devices.
See Documentation/arm/samsung-s3c24xx/overview.rst for more information
on the implementation details and specific support.
Configuration
-------------
......@@ -51,8 +40,6 @@ Layout
specific information. It contains the base clock, GPIO and device definitions
to get the system running.
plat-s3c24xx is for s3c24xx specific builds, see the S3C24XX docs.
plat-s5p is for s5p specific builds, and contains common support for the
S5P specific systems. Not all S5Ps use all the features in this directory
due to differences in the hardware.
......
Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt deleted 100644 → 0
View file @ 1027b4df
* Samsung S3C2410 Clock Controller
The S3C2410 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to the s3c2410,
s3c2440 and s3c2442 SoCs in the s3c24x family.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
- "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
- "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2410.h header and can be used in device
tree sources.
External clocks:
The xti clock used as input for the plls is generated outside the SoC. It is
expected that is are defined using standard clock bindings with a
clock-output-names value of "xti".
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2410-clock";
reg = <0x4c000000 0x20>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2440-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
};
Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt deleted 100644 → 0
View file @ 1027b4df
* Samsung S3C2412 Clock Controller
The S3C2412 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to the s3c2412
and s3c2413 SoCs in the s3c24x family.
Required Properties:
- compatible: should be "samsung,s3c2412-clock"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2412.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xti" - crystal input - required,
- "ext" - external clock source - optional,
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2412-clock";
reg = <0x4c000000 0x20>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2412-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
};
Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt deleted 100644 → 0
View file @ 1027b4df
* Samsung S3C2443 Clock Controller
The S3C2443 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to all SoCs in
the s3c24x family starting with the s3c2443.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
- "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
- "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2443.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xti" - crystal input - required,
- "ext" - external clock source - optional,
- "ext_i2s" - external I2S clock - optional,
- "ext_uart" - external uart clock - optional,
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2416-clock";
reg = <0x4c000000 0x40>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2440-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
};
Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt deleted 100644 → 0
View file @ 1027b4df
Samsung S3C24XX Interrupt Controllers
The S3C24XX SoCs contain a custom set of interrupt controllers providing a
varying number of interrupt sources. The set consists of a main- and sub-
controller and on newer SoCs even a second main controller.
Required properties:
- compatible: Compatible property value should be "samsung,s3c2410-irq"
for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
- reg: Physical base address of the controller and length of memory mapped
region.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 4 and interrupt descriptor shall
have the following format:
<ctrl_num parent_irq ctrl_irq type>
ctrl_num contains the controller to use:
- 0 ... main controller
- 1 ... sub controller
- 2 ... second main controller on s3c2416 and s3c2450
parent_irq contains the parent bit in the main controller and will be
ignored in main controllers
ctrl_irq contains the interrupt bit of the controller
type contains the trigger type to use
Example:
interrupt-controller@4a000000 {
compatible = "samsung,s3c2410-irq";
reg = <0x4a000000 0x100>;
interrupt-controller;
#interrupt-cells=<4>;
};
[...]
serial@50000000 {
compatible = "samsung,s3c2410-uart";
reg = <0x50000000 0x4000>;
interrupt-parent = <&subintc>;
interrupts = <1 28 0 4>, <1 28 1 4>;
};
rtc@57000000 {
compatible = "samsung,s3c2410-rtc";
reg = <0x57000000 0x100>;
interrupt-parent = <&intc>;
interrupts = <0 30 0 3>, <0 8 0 3>;
};
Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt deleted 100644 → 0
View file @ 1027b4df
* Samsung's S3C24XX MMC/SD/SDIO controller device tree bindings
Samsung's S3C24XX MMC/SD/SDIO controller is used as a connectivity interface
with external MMC, SD and SDIO storage mediums.
This file documents differences between the core mmc properties described by
mmc.txt and the properties used by the Samsung S3C24XX MMC/SD/SDIO controller
implementation.
Required SoC Specific Properties:
- compatible: should be one of the following
- "samsung,s3c2410-sdi": for controllers compatible with s3c2410
- "samsung,s3c2412-sdi": for controllers compatible with s3c2412
- "samsung,s3c2440-sdi": for controllers compatible with s3c2440
- reg: register location and length
- interrupts: mmc controller interrupt
- clocks: Should reference the controller clock
- clock-names: Should contain "sdi"
Required Board Specific Properties:
- pinctrl-0: Should specify pin control groups used for this controller.
- pinctrl-names: Should contain only one value - "default".
Optional Properties:
- bus-width: number of data lines (see mmc.txt)
- cd-gpios: gpio for card detection (see mmc.txt)
- wp-gpios: gpio for write protection (see mmc.txt)
Example:
mmc0: mmc@5a000000 {
compatible = "samsung,s3c2440-sdi";
pinctrl-names = "default";
pinctrl-0 = <&sdi_pins>;
reg = <0x5a000000 0x100000>;
interrupts = <0 0 21 3>;
clocks = <&clocks PCLK_SDI>;
clock-names = "sdi";
bus-width = <4>;
cd-gpios = <&gpg 8 GPIO_ACTIVE_LOW>;
wp-gpios = <&gph 8 GPIO_ACTIVE_LOW>;
};
MAINTAINERS
View file @ 61b7f892
......@@ -2583,13 +2583,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/dts/freescale/s32g*.dts*
ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT
L: openmoko-kernel@lists.openmoko.org (subscribers-only)
S: Orphan
W: http://wiki.openmoko.org/wiki/Neo_FreeRunner
F: arch/arm/mach-s3c/gta02.h
F: arch/arm/mach-s3c/mach-gta02.c
ARM/Orion SoC/Technologic Systems TS-78xx platform support
M: Alexander Clouter <alex@digriz.org.uk>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
......@@ -2796,7 +2789,6 @@ F: include/linux/platform_data/*s3c*
F: include/linux/serial_s3c.h
F: include/linux/soc/samsung/
N: exynos
N: s3c2410
N: s3c64xx
N: s5pv210
......@@ -19042,14 +19034,6 @@ M: Simtec Linux Team <linux@simtec.co.uk>
S: Supported
W: http://www.simtec.co.uk/products/EB110ATX/
SIMTEC EB2410ITX (BAST)
M: Simtec Linux Team <linux@simtec.co.uk>
S: Supported
W: http://www.simtec.co.uk/products/EB2410ITX/
F: arch/arm/mach-s3c/bast-ide.c
F: arch/arm/mach-s3c/bast-irq.c
F: arch/arm/mach-s3c/mach-bast.c
SIOX
M: Thorsten Scherer <t.scherer@eckelmann.de>
M: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
......
arch/arm/Kconfig
View file @ 61b7f892
......@@ -282,7 +282,6 @@ config PHYS_OFFSET
default DRAM_BASE if !MMU
default 0x00000000 if ARCH_FOOTBRIDGE
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
default 0x30000000 if ARCH_S3C24XX
default 0xa0000000 if ARCH_PXA
default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
default 0
......
arch/arm/Kconfig.debug
View file @ 61b7f892
......@@ -1006,7 +1006,6 @@ choice
config DEBUG_S3C_UART0
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 0 for low-level debug"
......@@ -1018,7 +1017,6 @@ choice
config DEBUG_S3C_UART1
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 1 for low-level debug"
......@@ -1030,7 +1028,6 @@ choice
config DEBUG_S3C_UART2
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 2 for low-level debug"
......@@ -1050,33 +1047,6 @@ choice
their output to UART 3. The port must have been initialised
by the boot-loader before use.
config DEBUG_S3C2410_UART0
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 0. The port must have been initialised
by the boot-loader before use.
config DEBUG_S3C2410_UART1
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 1. The port must have been initialised
by the boot-loader before use.
config DEBUG_S3C2410_UART2
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 2. The port must have been initialised
by the boot-loader before use.
config DEBUG_SA1100
depends on ARCH_SA1100
bool "Use SA1100 UARTs for low-level debug"
......@@ -1439,13 +1409,6 @@ config DEBUG_AT91_UART
config DEBUG_EXYNOS_UART
bool
config DEBUG_S3C2410_UART
bool
select DEBUG_S3C24XX_UART
config DEBUG_S3C24XX_UART
bool
config DEBUG_S3C64XX_UART
bool
......@@ -1453,8 +1416,7 @@ config DEBUG_S5PV210_UART
bool
config DEBUG_S3C_UART
depends on DEBUG_S3C2410_UART || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || DEBUG_S5PV210_UART || \
depends on DEBUG_S3C64XX_UART || DEBUG_S5PV210_UART || \
DEBUG_EXYNOS_UART
int
default "0" if DEBUG_S3C_UART0
......@@ -1555,7 +1517,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART || DEBUG_S3C64XX_UART
default "debug/s3c24xx.S" if DEBUG_S3C64XX_UART
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sti.S" if DEBUG_STIH41X_ASC2
default "debug/sti.S" if DEBUG_STIH41X_SBC_ASC1
......@@ -1638,12 +1600,6 @@ config DEBUG_UART_PHYS
default 0x4806e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4
default 0x49020000 if DEBUG_OMAP3UART3
default 0x49042000 if DEBUG_OMAP3UART4
default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
DEBUG_S3C2410_UART0)
default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
DEBUG_S3C2410_UART1)
default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2)
default 0x7c0003f8 if DEBUG_FOOTBRIDGE_COM1
default 0x7f005000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0
default 0x7f005400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1
......@@ -1711,7 +1667,7 @@ config DEBUG_UART_PHYS
DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
DEBUG_RCAR_GEN2_SCIFA2 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_RMOBILE_SCIFA4 || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_DIGICOLOR_UA0 || \
......@@ -1748,15 +1704,9 @@ config DEBUG_UART_VIRT
default 0xf6200000 if DEBUG_PXA_UART1
default 0xf7000000 if DEBUG_SUN9I_UART0
default 0xf7000000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0
default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
DEBUG_S3C2410_UART0)
default 0xf7000400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1
default 0xf7000800 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART2
default 0xf7000c00 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART3
default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
DEBUG_S3C2410_UART1)
default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2)
default 0xf7020000 if DEBUG_AT91_SAMA5D2_UART1
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8007000 if DEBUG_HIP04_UART
......@@ -1820,7 +1770,7 @@ config DEBUG_UART_VIRT
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
DEBUG_QCOM_UARTDM || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_DIGICOLOR_UA0 || \
......
arch/arm/Makefile
View file @ 61b7f892
......@@ -152,8 +152,6 @@ CHECKFLAGS += -D__arm__
# during boot, and this offset is critical to the functioning of
# kexec-tools.
textofs-y := 0x00008000
# We don't want the htc bootloader to corrupt kernel during resume
textofs-$(CONFIG_PM_H1940) := 0x00108000
# RTD1195 has Boot ROM at start of address space
textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000
# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
......
arch/arm/boot/dts/Makefile
View file @ 61b7f892
......@@ -1163,8 +1163,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-speedy.dtb \
rk3288-veyron-tiger.dtb \
rk3288-vyasa.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += \
s3c6410-mini6410.dtb \
s3c6410-smdk6410.dtb
......
arch/arm/boot/dts/s3c2410-pinctrl.h deleted 100644 → 0
View file @ 1027b4df
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Samsung S3C2410 DTS pinctrl constants
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2022 Linaro Ltd
* Author: Krzysztof Kozlowski <krzk@kernel.org>
*/
#ifndef __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__
#define __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__
#define S3C2410_PIN_FUNC_INPUT 0
#define S3C2410_PIN_FUNC_OUTPUT 1
#define S3C2410_PIN_FUNC_2 2
#define S3C2410_PIN_FUNC_3 3
#endif /* __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ */
arch/arm/boot/dts/s3c2416-pinctrl.dtsi deleted 100644 → 0
View file @ 1027b4df
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung S3C2416 pinctrl settings
*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*/
#include "s3c2410-pinctrl.h"
&pinctrl_0 {
/*
* Pin banks
*/
gpa: gpa-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
gpb: gpb-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
gpc: gpc-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
gpd: gpd-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
gpe: gpe-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
gpf: gpf-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg: gpg-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gph: gph-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
gpj: gpj-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
gpk: gpk-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
gpl: gpl-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
gpm: gpm-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
/*
* Pin groups
*/
uart0_data: uart0-data-pins {
samsung,pins = "gph-0", "gph-1";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
uart0_fctl: uart0-fctl-pins {
samsung,pins = "gph-8", "gph-9";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
uart1_data: uart1-data-pins {
samsung,pins = "gph-2", "gph-3";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
uart1_fctl: uart1-fctl-pins {
samsung,pins = "gph-10", "gph-11";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
uart2_data: uart2-data-pins {
samsung,pins = "gph-4", "gph-5";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
uart2_fctl: uart2-fctl-pins {
samsung,pins = "gph-6", "gph-7";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
uart3_data: uart3-data-pins {
samsung,pins = "gph-6", "gph-7";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
extuart_clk: extuart-clk-pins {
samsung,pins = "gph-12";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
i2c0_bus: i2c0-bus-pins {
samsung,pins = "gpe-14", "gpe-15";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
spi0_bus: spi0-bus-pins {
samsung,pins = "gpe-11", "gpe-12", "gpe-13";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
sd0_clk: sd0-clk-pins {
samsung,pins = "gpe-5";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
sd0_cmd: sd0-cmd-pins {
samsung,pins = "gpe-6";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
sd0_bus1: sd0-bus1-pins {
samsung,pins = "gpe-7";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
sd0_bus4: sd0-bus4-pins {
samsung,pins = "gpe-8", "gpe-9", "gpe-10";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
sd1_cmd: sd1-cmd-pins {
samsung,pins = "gpl-8";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
sd1_clk: sd1-clk-pins {
samsung,pins = "gpl-9";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
sd1_bus1: sd1-bus1-pins {
samsung,pins = "gpl-0";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
sd1_bus4: sd1-bus4-pins {
samsung,pins = "gpl-1", "gpl-2", "gpl-3";
samsung,pin-function = <S3C2410_PIN_FUNC_2>;
};
};
arch/arm/boot/dts/s3c2416-smdk2416.dts deleted 100644 → 0
View file @ 1027b4df
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung SMDK2416 board device tree source
*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*/
/dts-v1/;
#include "s3c2416.dtsi"
/ {
model = "SMDK2416";
compatible = "samsung,smdk2416", "samsung,s3c2416";
memory@30000000 {
device_type = "memory";
reg = <0x30000000 0x4000000>;
};
xti: clock-0 {
compatible = "fixed-clock";
clock-frequency = <12000000>;
clock-output-names = "xti";
#clock-cells = <0>;
};
};
&rtc {
status = "okay";
};
&sdhci_0 {
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk>, <&sd1_cmd>,
<&sd1_bus1>, <&sd1_bus4>;
bus-width = <4>;
broken-cd;
status = "okay";
};
&sdhci_1 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>,
<&sd0_bus1>, <&sd0_bus4>;
bus-width = <4>;
cd-gpios = <&gpf 1 0>;
cd-inverted;
status = "okay";
};
&uart_0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
};
&uart_1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
};
&uart_2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2_data>;
};
&uart_3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3_data>;
};
&watchdog {
status = "okay";
};
arch/arm/boot/dts/s3c2416.dtsi deleted 100644 → 0
View file @ 1027b4df
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's S3C2416 SoC device tree source
*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*/
#include <dt-bindings/clock/s3c2443.h>
#include "s3c24xx.dtsi"
#include "s3c2416-pinctrl.dtsi"
/ {
model = "Samsung S3C2416 SoC";
compatible = "samsung,s3c2416";
aliases {
serial3 = &uart_3;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,arm926ej-s";
reg = <0x0>;
};
};
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2416-clock";
reg = <0x4c000000 0x40>;
#clock-cells = <1>;
};
uart_3: serial@5000c000 {
compatible = "samsung,s3c2440-uart";
reg = <0x5000C000 0x4000>;
interrupts = <1 18 24 4>, <1 18 25 4>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
<&clocks SCLK_UART>;
status = "disabled";
};
sdhci_1: mmc@4ac00000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x4AC00000 0x100>;
interrupts = <0 0 21 3>;
clock-names = "hsmmc", "mmc_busclk.0",
"mmc_busclk.2";
clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
<&clocks MUX_HSMMC0>;
status = "disabled";
};
sdhci_0: mmc@4a800000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x4A800000 0x100>;
interrupts = <0 0 20 3>;
clock-names = "hsmmc", "mmc_busclk.0",
"mmc_busclk.2";
clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
<&clocks MUX_HSMMC1>;
status = "disabled";
};
};
&i2c {
compatible = "samsung,s3c2440-i2c";
clocks = <&clocks PCLK_I2C0>;
clock-names = "i2c";
};
&intc {
compatible = "samsung,s3c2416-irq";
};
&pinctrl_0 {
compatible = "samsung,s3c2416-pinctrl";
};
&rtc {
compatible = "samsung,s3c2416-rtc";
clocks = <&clocks PCLK_RTC>;
clock-names = "rtc";
};
&timer {
clocks = <&clocks PCLK_PWM>;
clock-names = "timers";
};
&uart_0 {
compatible = "samsung,s3c2440-uart";
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
};
&uart_1 {
compatible = "samsung,s3c2440-uart";
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
<&clocks SCLK_UART>;
};
&uart_2 {
compatible = "samsung,s3c2440-uart";
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
<&clocks SCLK_UART>;
};
&watchdog {
interrupts = <1 9 27 3>;
clocks = <&clocks PCLK_WDT>;
clock-names = "watchdog";
};
arch/arm/boot/dts/s3c24xx.dtsi deleted 100644 → 0
View file @ 1027b4df
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's S3C24XX family device tree source
*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*/
/ {
compatible = "samsung,s3c24xx";
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
aliases {
pinctrl0 = &pinctrl_0;
serial0 = &uart_0;
serial1 = &uart_1;
serial2 = &uart_2;
};
intc: interrupt-controller@4a000000 {
compatible = "samsung,s3c2410-irq";
reg = <0x4a000000 0x100>;
interrupt-controller;
#interrupt-cells = <4>;
};
pinctrl_0: pinctrl@56000000 {
reg = <0x56000000 0x1000>;
wakeup-interrupt-controller {
compatible = "samsung,s3c2410-wakeup-eint";
interrupts = <0 0 0 3>,
<0 0 1 3>,
<0 0 2 3>,
<0 0 3 3>,
<0 0 4 4>,
<0 0 5 4>;
};
};
timer: pwm@51000000 {
compatible = "samsung,s3c2410-pwm";
reg = <0x51000000 0x1000>;
interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>;
#pwm-cells = <3>;
};
uart_0: serial@50000000 {
compatible = "samsung,s3c2410-uart";
reg = <0x50000000 0x4000>;
interrupts = <1 28 0 4>, <1 28 1 4>;
status = "disabled";
};
uart_1: serial@50004000 {
compatible = "samsung,s3c2410-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
status = "disabled";
};
uart_2: serial@50008000 {
compatible = "samsung,s3c2410-uart";
reg = <0x50008000 0x4000>;
interrupts = <1 15 6 4>, <1 15 7 4>;
status = "disabled";
};
watchdog: watchdog@53000000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x53000000 0x100>;
interrupts = <0 0 9 3>;
status = "disabled";
};
rtc: rtc@57000000 {
compatible = "samsung,s3c2410-rtc";
reg = <0x57000000 0x100>;
interrupts = <0 0 30 3>, <0 0 8 3>;
status = "disabled";
};
i2c: i2c@54000000 {
compatible = "samsung,s3c2410-i2c";
reg = <0x54000000 0x100>;
interrupts = <0 0 27 3>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
arch/arm/configs/mini2440_defconfig deleted 100644 → 0
View file @ 1027b4df
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_ARCH_MULTI_V4T=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_S3C24XX=y
CONFIG_S3C_ADC=y
# CONFIG_CPU_S3C2410 is not set
CONFIG_CPU_S3C2440=y
CONFIG_MACH_MINI2440=y
CONFIG_AEABI=y
CONFIG_UNUSED_BOARD_FILES=y
CONFIG_KEXEC=y
CONFIG_CPU_IDLE=y
CONFIG_APM_EMULATION=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
CONFIG_LDM_PARTITION=y
CONFIG_BINFMT_MISC=m
# CONFIG_COMPAT_BRK is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_NET_KEY=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_INET_DIAG=m
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_NET_PKTGEN=m
CONFIG_BT=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_BT_HCIBTUSB=m
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_CFG80211=m
CONFIG_MAC80211=m
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
CONFIG_CONNECTOR=m
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_FTL=y
CONFIG_NFTL=y
CONFIG_NFTL_RW=y
CONFIG_INFTL=y
CONFIG_RFD_FTL=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_S3C2410=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_LPDDR=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_CDROM_PKTCDVD=m
CONFIG_SENSORS_TSL2550=m
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=m
CONFIG_CHR_DEV_SG=m
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_TUN=m
CONFIG_DM9000=y
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_HOSTAP=m
CONFIG_HOSTAP_FIRMWARE=y
CONFIG_HOSTAP_FIRMWARE_NVRAM=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_ZD1211RW=m
CONFIG_ZD1211RW_DEBUG=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=m
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIO_RAW=y
CONFIG_LEGACY_PTY_COUNT=128
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=m
CONFIG_IPMI_HANDLER=m
CONFIG_IPMI_DEVICE_INTERFACE=m
CONFIG_IPMI_SI=m
CONFIG_IPMI_WATCHDOG=m
CONFIG_IPMI_POWEROFF=m
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_S3C2410=y
CONFIG_I2C_SIMTEC=y
CONFIG_SPI=y
CONFIG_SPI_S3C24XX=y
CONFIG_SPI_SPIDEV=y
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_LM75=y
CONFIG_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_S3C2410_WATCHDOG=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
CONFIG_FB_S3C2410=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_SOC=y
CONFIG_HIDRAW=y
CONFIG_HID_GYRATION=y
CONFIG_HID_NTRIG=y
CONFIG_HID_PANTHERLORD=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
CONFIG_HID_SUNPLUS=y
CONFIG_HID_TOPSEED=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_ACM=m
CONFIG_USB_WDM=m
CONFIG_USB_STORAGE=m
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_GADGET=y
CONFIG_USB_S3C2410=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
CONFIG_SDIO_UART=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SPI=y
CONFIG_MMC_S3C=y
CONFIG_LEDS_S3C24XX=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_DRV_S3C=y
CONFIG_DMADEVICES=y
CONFIG_S3C24XX_DMAC=y
CONFIG_PWM=y
CONFIG_PWM_SAMSUNG=y
CONFIG_EXT2_FS=m
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_BOTH=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="cp437"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_CTS=m
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_RMD128=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_RMD256=m
CONFIG_CRYPTO_RMD320=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_LZO=m
CONFIG_LIBCRC32C=m
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_MINI_4x6=y
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_DEBUG_USER=y
arch/arm/configs/s3c2410_defconfig deleted 100644 → 0
View file @ 1027b4df
This diff is collapsed.
arch/arm/configs/tct_hammer_defconfig deleted 100644 → 0
View file @ 1027b4df
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_ELF_CORE is not set
# CONFIG_SHMEM is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_KALLSYMS is not set
CONFIG_ARCH_MULTI_V4T=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_S3C24XX=y
CONFIG_MACH_TCT_HAMMER=y
CONFIG_UNUSED_BOARD_FILES=y
CONFIG_CMDLINE="mem=64M root=/dev/ram0 init=/linuxrc rw"
CONFIG_FPE_NWFPE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_SWAP is not set
CONFIG_SLUB=y
CONFIG_SLUB_TINY=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=10240
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT_CONSOLE is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_S3C2410=y
CONFIG_USB_ETH=m
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
# CONFIG_PROC_SYSCTL is not set
CONFIG_JFFS2_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_CRC_CCITT=y
CONFIG_DEBUG_LL=y
arch/arm/mach-s3c/Kconfig
View file @ 61b7f892
......@@ -2,13 +2,10 @@
#
# Copyright 2009 Simtec Electronics
source "arch/arm/mach-s3c/Kconfig.s3c24xx"
source "arch/arm/mach-s3c/Kconfig.s3c64xx"
config PLAT_SAMSUNG
bool
depends on PLAT_S3C24XX || ARCH_S3C64XX
default y
def_bool ARCH_S3C64XX
select GENERIC_IRQ_CHIP
select NO_IOPORT_MAP
select SOC_SAMSUNG
......@@ -16,9 +13,8 @@ config PLAT_SAMSUNG
Base platform code for all Samsung SoC based systems
config SAMSUNG_PM
bool
depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX)
default y
def_bool ARCH_S3C64XX
depends on PM
help
Base platform power management code for samsung code
......@@ -99,11 +95,6 @@ config S3C_DEV_HSMMC3
help
Compile in platform device definitions for HSMMC channel 3
config S3C_DEV_HWMON
bool
help
Compile in platform device definitions for HWMON
config S3C_DEV_I2C1
bool
help
......@@ -156,7 +147,6 @@ config S3C_DEV_USB_HSOTG
config S3C_DEV_WDT
bool
default y if ARCH_S3C24XX
help
Compile in platform device definition for Watchdog Timer
......@@ -180,22 +170,12 @@ config SAMSUNG_DEV_ADC
help
Compile in platform device definition for ADC controller
config SAMSUNG_DEV_IDE
bool
help
Compile in platform device definitions for IDE
config S3C64XX_DEV_SPI0
bool
help
Compile in platform device definitions for S3C64XX's type
SPI controller 0
config SAMSUNG_DEV_TS
bool
help
Common in platform device definitions for touchscreen device
config SAMSUNG_DEV_KEYPAD
bool
help
......@@ -203,7 +183,6 @@ config SAMSUNG_DEV_KEYPAD
config SAMSUNG_DEV_PWM
bool
default y if ARCH_S3C24XX
help
Compile in platform device definition for PWM Timer
......
arch/arm/mach-s3c/Kconfig.s3c24xx deleted 100644 → 0
View file @ 1027b4df
This diff is collapsed.
arch/arm/mach-s3c/Makefile
View file @ 61b7f892
......@@ -2,10 +2,6 @@
#
# Copyright 2009 Simtec Electronics
ifdef CONFIG_ARCH_S3C24XX
include $(src)/Makefile.s3c24xx
endif
ifdef CONFIG_ARCH_S3C64XX
include $(src)/Makefile.s3c64xx
endif
......
arch/arm/mach-s3c/Makefile.s3c24xx deleted 100644 → 0
View file @ 1027b4df
# SPDX-License-Identifier: GPL-2.0
#
# Copyright (c) 2012 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Copyright 2007 Simtec Electronics
# core
obj-y += s3c24xx.o
obj-y += irq-s3c24xx.o
obj-$(CONFIG_SPI_S3C24XX_FIQ) += irq-s3c24xx-fiq.o
obj-$(CONFIG_SPI_S3C24XX_FIQ) += irq-s3c24xx-fiq-exports.o
obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o
obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
obj-$(CONFIG_CPU_S3C2416) += s3c2416.o
obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o
obj-$(CONFIG_CPU_S3C2440) += s3c2440.o
obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
obj-$(CONFIG_CPU_S3C2443) += s3c2443.o
# PM
obj-$(CONFIG_PM) += pm-s3c24xx.o
obj-$(CONFIG_PM_SLEEP) += irq-pm-s3c24xx.o sleep-s3c24xx.o
# common code
obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += cpufreq-utils-s3c24xx.o
obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
#
# machine support
# following is ordered alphabetically by option text.
#
obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o
obj-$(CONFIG_ARCH_BAST) += mach-bast.o
obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o
obj-$(CONFIG_ARCH_H1940) += mach-h1940.o
obj-$(CONFIG_H1940BT) += h1940-bluetooth.o
obj-$(CONFIG_PM_H1940) += pm-h1940.o
obj-$(CONFIG_MACH_N30) += mach-n30.o
obj-$(CONFIG_MACH_OTOM) += mach-otom.o
obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o
obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o
obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o
obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o
obj-$(CONFIG_MACH_JIVE) += mach-jive.o
obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o
obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o
obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o
obj-$(CONFIG_MACH_S3C2416_DT) += mach-s3c2416-dt.o
obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o
obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o
obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o
obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o
obj-$(CONFIG_MACH_SMDK2443) += mach-smdk2443.o
# common bits of machine support
obj-$(CONFIG_S3C24XX_SMDK) += common-smdk-s3c24xx.o
obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO) += simtec-audio.o
obj-$(CONFIG_S3C24XX_SIMTEC_NOR) += simtec-nor.o
obj-$(CONFIG_S3C24XX_SIMTEC_PM) += simtec-pm.o
obj-$(CONFIG_S3C24XX_SIMTEC_USB) += simtec-usb.o
# machine additions
obj-$(CONFIG_MACH_BAST_IDE) += bast-ide.o
obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o
# device setup
obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio-s3c24xx.o
obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi-s3c24xx.o
obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c-s3c24xx.o
obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts-s3c24xx.o
arch/arm/mach-s3c/anubis.h deleted 100644 → 0
View file @ 1027b4df
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2005 Simtec Electronics
* http://www.simtec.co.uk/products/
* Ben Dooks <ben@simtec.co.uk>
*
* ANUBIS - CPLD control constants
* ANUBIS - IRQ Number definitions
* ANUBIS - Memory map definitions
*/
#ifndef __MACH_S3C24XX_ANUBIS_H
#define __MACH_S3C24XX_ANUBIS_H __FILE__
/* CTRL2 - NAND WP control, IDE Reset assert/check */
#define ANUBIS_CTRL1_NANDSEL (0x3)
/* IDREG - revision */
#define ANUBIS_IDREG_REVMASK (0x7)
/* irq */
#define ANUBIS_IRQ_IDE0 IRQ_EINT2
#define ANUBIS_IRQ_IDE1 IRQ_EINT3
#define ANUBIS_IRQ_ASIX IRQ_EINT1
/* map */
/* start peripherals off after the S3C2410 */
#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
/* we put the CPLD registers next, to get them out of the way */
#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000)
#define ANUBIS_PA_CTRL1 ANUBIS_PA_CPLD
#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000)
#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3 << 23))
#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
#endif /* __MACH_S3C24XX_ANUBIS_H */
arch/arm/mach-s3c/bast-ide.c deleted 100644 → 0
View file @ 1027b4df
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2007 Simtec Electronics
// http://www.simtec.co.uk/products/EB2410ITX/
// http://armlinux.simtec.co.uk/
// Ben Dooks <ben@simtec.co.uk>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include "map.h"
#include "irqs.h"
#include "bast.h"
/* IDE ports */
static struct pata_platform_info bast_ide_platdata = {
.ioport_shift = 5,
};
static struct resource bast_ide0_resource[] = {
[0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
[1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
[2] = DEFINE_RES_IRQ(BAST_IRQ_IDE0),
};
static struct platform_device bast_device_ide0 = {
.name = "pata_platform",
.id = 0,
.num_resources = ARRAY_SIZE(bast_ide0_resource),
.resource = bast_ide0_resource,
.dev = {
.platform_data = &bast_ide_platdata,
.coherent_dma_mask = ~0,
}
};
static struct resource bast_ide1_resource[] = {
[0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
[1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
[2] = DEFINE_RES_IRQ(BAST_IRQ_IDE1),
};
static struct platform_device bast_device_ide1 = {
.name = "pata_platform",
.id = 1,
.num_resources = ARRAY_SIZE(bast_ide1_resource),
.resource = bast_ide1_resource,
.dev = {
.platform_data = &bast_ide_platdata,
.coherent_dma_mask = ~0,
}
};
static struct platform_device *bast_ide_devices[] __initdata = {
&bast_device_ide0,
&bast_device_ide1,
};
static __init int bast_ide_init(void)
{
if (machine_is_bast() || machine_is_vr1000())
return platform_add_devices(bast_ide_devices,
ARRAY_SIZE(bast_ide_devices));
return 0;
}
fs_initcall(bast_ide_init);
arch/arm/mach-s3c/bast-irq.c deleted 100644 → 0
View file @ 1027b4df
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2003-2005 Simtec Electronics
// Ben Dooks <ben@simtec.co.uk>
//
// http://www.simtec.co.uk/products/EB2410ITX/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/irq.h>
#include "regs-irq.h"
#include "irqs.h"
#include "bast.h"
#define irqdbf(x...)
#define irqdbf2(x...)
/* handle PC104 ISA interrupts from the system CPLD */
/* table of ISA irq nos to the relevant mask... zero means
* the irq is not implemented
*/
static const unsigned char bast_pc104_irqmasks[] = {
0, /* 0 */
0, /* 1 */
0, /* 2 */
1, /* 3 */
0, /* 4 */
2, /* 5 */
0, /* 6 */
4, /* 7 */
0, /* 8 */
0, /* 9 */
8, /* 10 */
0, /* 11 */
0, /* 12 */
0, /* 13 */
0, /* 14 */
0, /* 15 */
};
static const unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 };
static void
bast_pc104_mask(struct irq_data *data)
{
unsigned long temp;
temp = __raw_readb(BAST_VA_PC104_IRQMASK);
temp &= ~bast_pc104_irqmasks[data->irq];
__raw_writeb(temp, BAST_VA_PC104_IRQMASK);
}
static void
bast_pc104_maskack(struct irq_data *data)
{
struct irq_desc *desc = irq_to_desc(BAST_IRQ_ISA);
bast_pc104_mask(data);
desc->irq_data.chip->irq_ack(&desc->irq_data);
}
static void
bast_pc104_unmask(struct irq_data *data)
{
unsigned long temp;
temp = __raw_readb(BAST_VA_PC104_IRQMASK);
temp |= bast_pc104_irqmasks[data->irq];
__raw_writeb(temp, BAST_VA_PC104_IRQMASK);
}
static struct irq_chip bast_pc104_chip = {
.irq_mask = bast_pc104_mask,
.irq_unmask = bast_pc104_unmask,
.irq_ack = bast_pc104_maskack
};
static void bast_irq_pc104_demux(struct irq_desc *desc)
{
unsigned int stat;
unsigned int irqno;
int i;
stat = __raw_readb(BAST_VA_PC104_IRQREQ) & 0xf;
if (unlikely(stat == 0)) {
/* ack if we get an irq with nothing (ie, startup) */
desc->irq_data.chip->irq_ack(&desc->irq_data);
} else {
/* handle the IRQ */
for (i = 0; stat != 0; i++, stat >>= 1) {
if (stat & 1) {
irqno = bast_pc104_irqs[i];
generic_handle_irq(irqno);
}
}
}
}
static __init int bast_irq_init(void)
{
unsigned int i;
if (machine_is_bast()) {
printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n");
/* zap all the IRQs */
__raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux);
/* register our IRQs */
for (i = 0; i < 4; i++) {
unsigned int irqno = bast_pc104_irqs[i];
irq_set_chip_and_handler(irqno, &bast_pc104_chip,
handle_level_irq);
irq_clear_status_flags(irqno, IRQ_NOREQUEST);
}
}
return 0;
}
arch_initcall(bast_irq_init);
arch/arm/mach-s3c/bast.h deleted 100644 → 0
View file @ 1027b4df
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* BAST - CPLD control constants
* BAST - IRQ Number definitions
* BAST - Memory map definitions
*/
#ifndef __MACH_S3C24XX_BAST_H
#define __MACH_S3C24XX_BAST_H __FILE__
/* CTRL1 - Audio LR routing */
#define BAST_CPLD_CTRL1_LRCOFF (0x00)
#define BAST_CPLD_CTRL1_LRCADC (0x01)
#define BAST_CPLD_CTRL1_LRCDAC (0x02)
#define BAST_CPLD_CTRL1_LRCARM (0x03)
#define BAST_CPLD_CTRL1_LRMASK (0x03)
/* CTRL2 - NAND WP control, IDE Reset assert/check */
#define BAST_CPLD_CTRL2_WNAND (0x04)
#define BAST_CPLD_CTLR2_IDERST (0x08)
/* CTRL3 - rom write control, CPLD identity */
#define BAST_CPLD_CTRL3_IDMASK (0x0e)
#define BAST_CPLD_CTRL3_ROMWEN (0x01)
/* CTRL4 - 8bit LCD interface control/status */
#define BAST_CPLD_CTRL4_LLAT (0x01)
#define BAST_CPLD_CTRL4_LCDRW (0x02)
#define BAST_CPLD_CTRL4_LCDCMD (0x04)
#define BAST_CPLD_CTRL4_LCDE2 (0x01)
/* CTRL5 - DMA routing */
#define BAST_CPLD_DMA0_PRIIDE (0)
#define BAST_CPLD_DMA0_SECIDE (1)
#define BAST_CPLD_DMA0_ISA15 (2)
#define BAST_CPLD_DMA0_ISA36 (3)
#define BAST_CPLD_DMA1_PRIIDE (0 << 2)
#define BAST_CPLD_DMA1_SECIDE (1 << 2)
#define BAST_CPLD_DMA1_ISA15 (2 << 2)
#define BAST_CPLD_DMA1_ISA36 (3 << 2)
/* irq numbers to onboard peripherals */
#define BAST_IRQ_USBOC IRQ_EINT18
#define BAST_IRQ_IDE0 IRQ_EINT16
#define BAST_IRQ_IDE1 IRQ_EINT17
#define BAST_IRQ_PCSERIAL1 IRQ_EINT15
#define BAST_IRQ_PCSERIAL2 IRQ_EINT14
#define BAST_IRQ_PCPARALLEL IRQ_EINT13
#define BAST_IRQ_ASIX IRQ_EINT11
#define BAST_IRQ_DM9000 IRQ_EINT10
#define BAST_IRQ_ISA IRQ_EINT9
#define BAST_IRQ_SMALERT IRQ_EINT8
/* map */
/*
* ok, we've used up to 0x13000000, now we need to find space for the
* peripherals that live in the nGCS[x] areas, which are quite numerous
* in their space. We also have the board's CPLD to find register space
* for.
*/
#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
/* we put the CPLD registers next, to get them out of the way */
#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000)
#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000)
#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000)
#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000)
#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
/* next, we have the PC104 ISA interrupt registers */
#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000)
#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000)
#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000)
#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
#define BAST_PA_LCD_RCMD1 (0x8800000)
#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
#define BAST_PA_LCD_WCMD1 (0x8000000)
#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
#define BAST_PA_LCD_RDATA1 (0x9800000)
#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
#define BAST_PA_LCD_WDATA1 (0x9000000)
#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
#define BAST_PA_LCD_RCMD2 (0xA800000)
#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
#define BAST_PA_LCD_WCMD2 (0xA000000)
#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
#define BAST_PA_LCD_RDATA2 (0xB800000)
#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
#define BAST_PA_LCD_WDATA2 (0xB000000)
#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
/*
* 0xE0000000 contains the IO space that is split by speed and
* whether the access is for 8 or 16bit IO... this ensures that
* the correct access is made
*
* 0x10000000 of space, partitioned as so:
*
* 0x00000000 to 0x04000000 8bit, slow
* 0x04000000 to 0x08000000 16bit, slow
* 0x08000000 to 0x0C000000 16bit, net
* 0x0C000000 to 0x10000000 16bit, fast
*
* each of these spaces has the following in:
*
* 0x00000000 to 0x01000000 16MB ISA IO space
* 0x01000000 to 0x02000000 16MB ISA memory space
* 0x02000000 to 0x02100000 1MB IDE primary channel
* 0x02100000 to 0x02200000 1MB IDE primary channel aux
* 0x02200000 to 0x02400000 1MB IDE secondary channel
* 0x02300000 to 0x02400000 1MB IDE secondary channel aux
* 0x02400000 to 0x02500000 1MB ASIX ethernet controller
* 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
* 0x02600000 to 0x02700000 1MB PC SuperIO controller
*
* the phyiscal layout of the zones are:
* nGCS2 - 8bit, slow
* nGCS3 - 16bit, slow
* nGCS4 - 16bit, net
* nGCS5 - 16bit, fast
*/
#define BAST_VA_MULTISPACE (0xE0000000)
#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
#define BAST_VAM_CS2 (0x00000000)
#define BAST_VAM_CS3 (0x04000000)
#define BAST_VAM_CS4 (0x08000000)
#define BAST_VAM_CS5 (0x0C000000)
/* physical offset addresses for the peripherals */
#define BAST_PA_ISAIO (0x00000000)
#define BAST_PA_ASIXNET (0x01000000)
#define BAST_PA_SUPERIO (0x01800000)
#define BAST_PA_IDEPRI (0x02000000)
#define BAST_PA_IDEPRIAUX (0x02800000)
#define BAST_PA_IDESEC (0x03000000)
#define BAST_PA_IDESECAUX (0x03800000)
#define BAST_PA_ISAMEM (0x04000000)
#define BAST_PA_DM9000 (0x05000000)
/* some configurations for the peripherals */
#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
#define BAST_ASIXNET_CS BAST_VAM_CS5
#define BAST_DM9000_CS BAST_VAM_CS4
#define BAST_IDE_CS S3C2410_CS5
#endif /* __MACH_S3C24XX_BAST_H */
arch/arm/mach-s3c/common-smdk-s3c24xx.c deleted 100644 → 0
View file @ 1027b4df
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2006 Simtec Electronics
// Ben Dooks <ben@simtec.co.uk>
//
// Common code for SMDK2410 and SMDK2440 boards
//
// http://www.fluff.org/ben/smdk2440/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/nand-ecc-sw-hamming.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include "regs-gpio.h"
#include "gpio-samsung.h"
#include <linux/platform_data/leds-s3c24xx.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include "gpio-cfg.h"
#include "devs.h"
#include "pm.h"
#include "common-smdk-s3c24xx.h"
/* LED devices */
static struct gpiod_lookup_table smdk_led4_gpio_table = {
.dev_id = "s3c24xx_led.0",
.table = {
GPIO_LOOKUP("GPF", 4, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
{ },
},
};
static struct gpiod_lookup_table smdk_led5_gpio_table = {
.dev_id = "s3c24xx_led.1",
.table = {
GPIO_LOOKUP("GPF", 5, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
{ },
},
};
static struct gpiod_lookup_table smdk_led6_gpio_table = {
.dev_id = "s3c24xx_led.2",
.table = {
GPIO_LOOKUP("GPF", 6, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
{ },
},
};
static struct gpiod_lookup_table smdk_led7_gpio_table = {
.dev_id = "s3c24xx_led.3",
.table = {
GPIO_LOOKUP("GPF", 7, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
{ },
},
};
static struct s3c24xx_led_platdata smdk_pdata_led4 = {
.name = "led4",
.def_trigger = "timer",
};
static struct s3c24xx_led_platdata smdk_pdata_led5 = {
.name = "led5",
.def_trigger = "nand-disk",
};
static struct s3c24xx_led_platdata smdk_pdata_led6 = {
.name = "led6",
};
static struct s3c24xx_led_platdata smdk_pdata_led7 = {
.name = "led7",
};
static struct platform_device smdk_led4 = {
.name = "s3c24xx_led",
.id = 0,
.dev = {
.platform_data = &smdk_pdata_led4,
},
};
static struct platform_device smdk_led5 = {
.name = "s3c24xx_led",
.id = 1,
.dev = {
.platform_data = &smdk_pdata_led5,
},
};
static struct platform_device smdk_led6 = {
.name = "s3c24xx_led",
.id = 2,
.dev = {
.platform_data = &smdk_pdata_led6,
},
};
static struct platform_device smdk_led7 = {
.name = "s3c24xx_led",
.id = 3,
.dev = {
.platform_data = &smdk_pdata_led7,
},
};
/* NAND parititon from 2.4.18-swl5 */
static struct mtd_partition smdk_default_nand_part[] = {
[0] = {
.name = "Boot Agent",
.size = SZ_16K,
.offset = 0,
},
[1] = {
.name = "S3C2410 flash partition 1",
.offset = 0,
.size = SZ_2M,
},
[2] = {
.name = "S3C2410 flash partition 2",
.offset = SZ_4M,
.size = SZ_4M,
},
[3] = {
.name = "S3C2410 flash partition 3",
.offset = SZ_8M,
.size = SZ_2M,
},
[4] = {
.name = "S3C2410 flash partition 4",
.offset = SZ_1M * 10,
.size = SZ_4M,
},
[5] = {
.name = "S3C2410 flash partition 5",
.offset = SZ_1M * 14,
.size = SZ_1M * 10,
},
[6] = {
.name = "S3C2410 flash partition 6",
.offset = SZ_1M * 24,
.size = SZ_1M * 24,
},
[7] = {
.name = "S3C2410 flash partition 7",
.offset = SZ_1M * 48,
.size = MTDPART_SIZ_FULL,
}
};
static struct s3c2410_nand_set smdk_nand_sets[] = {
[0] = {
.name = "NAND",
.nr_chips = 1,
.nr_partitions = ARRAY_SIZE(smdk_default_nand_part),
.partitions = smdk_default_nand_part,
},
};
/* choose a set of timings which should suit most 512Mbit
* chips and beyond.
*/
static struct s3c2410_platform_nand smdk_nand_info = {
.tacls = 20,
.twrph0 = 60,
.twrph1 = 20,
.nr_sets = ARRAY_SIZE(smdk_nand_sets),
.sets = smdk_nand_sets,
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
/* devices we initialise */
static struct platform_device __initdata *smdk_devs[] = {
&s3c_device_nand,
&smdk_led4,
&smdk_led5,
&smdk_led6,
&smdk_led7,
};
void __init smdk_machine_init(void)
{
if (machine_is_smdk2443())
smdk_nand_info.twrph0 = 50;
s3c_nand_set_platdata(&smdk_nand_info);
/* Disable pull-up on the LED lines */
s3c_gpio_setpull(S3C2410_GPF(4), S3C_GPIO_PULL_NONE);
s3c_gpio_setpull(S3C2410_GPF(5), S3C_GPIO_PULL_NONE);
s3c_gpio_setpull(S3C2410_GPF(6), S3C_GPIO_PULL_NONE);
s3c_gpio_setpull(S3C2410_GPF(7), S3C_GPIO_PULL_NONE);
/* Add lookups for the lines */
gpiod_add_lookup_table(&smdk_led4_gpio_table);
gpiod_add_lookup_table(&smdk_led5_gpio_table);
gpiod_add_lookup_table(&smdk_led6_gpio_table);
gpiod_add_lookup_table(&smdk_led7_gpio_table);
platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
s3c_pm_init();
}
arch/arm/mach-s3c/common-smdk-s3c24xx.h deleted 100644 → 0
View file @ 1027b4df
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Common code for SMDK2410 and SMDK2440 boards
*
* http://www.fluff.org/ben/smdk2440/
*/
extern void smdk_machine_init(void);
arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c deleted 100644 → 0
View file @ 1027b4df
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2009 Simtec Electronics
// http://armlinux.simtec.co.uk/
// Ben Dooks <ben@simtec.co.uk>
//
// S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/cpufreq.h>
#include <linux/io.h>
#include <linux/clk.h>
#include "map.h"
#include "regs-clock.h"
#include <linux/soc/samsung/s3c-cpufreq-core.h>
#include "regs-mem-s3c24xx.h"
/**
* s3c2410_cpufreq_setrefresh - set SDRAM refresh value
* @cfg: The frequency configuration
*
* Set the SDRAM refresh value appropriately for the configured
* frequency.
*/
void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
{
struct s3c_cpufreq_board *board = cfg->board;
unsigned long refresh;
unsigned long refval;
/* Reduce both the refresh time (in ns) and the frequency (in MHz)
* down to ensure that we do not overflow 32 bit numbers.
*
* This should work for HCLK up to 133MHz and refresh period up
* to 30usec.
*/
refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
refresh = (1 << 11) + 1 - refresh;
s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
refval = __raw_readl(S3C2410_REFRESH);
refval &= ~((1 << 12) - 1);
refval |= refresh;
__raw_writel(refval, S3C2410_REFRESH);
}
/**
* s3c2410_set_fvco - set the PLL value
* @cfg: The frequency configuration
*/
void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
{
if (!IS_ERR(cfg->mpll))
clk_set_rate(cfg->mpll, cfg->pll.frequency);
}
#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
u32 s3c2440_read_camdivn(void)
{
return __raw_readl(S3C2440_CAMDIVN);
}
void s3c2440_write_camdivn(u32 camdiv)
{
__raw_writel(camdiv, S3C2440_CAMDIVN);
}
#endif
u32 s3c24xx_read_clkdivn(void)
{
return __raw_readl(S3C2410_CLKDIVN);
}
void s3c24xx_write_clkdivn(u32 clkdiv)
{
__raw_writel(clkdiv, S3C2410_CLKDIVN);
}
u32 s3c24xx_read_mpllcon(void)
{
return __raw_readl(S3C2410_MPLLCON);
}
void s3c24xx_write_locktime(u32 locktime)
{
return __raw_writel(locktime, S3C2410_LOCKTIME);
}
arch/arm/mach-s3c/dma-s3c24xx.h deleted 100644 → 0
View file @ 1027b4df
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2003-2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C24XX DMA support
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__
#include <linux/device.h>
/* We use `virtual` dma channels to hide the fact we have only a limited
* number of DMA channels, and not of all of them (dependent on the device)
* can be attached to any DMA source. We therefore let the DMA core handle
* the allocation of hardware channels to clients.
*/
enum dma_ch {
DMACH_XD0 = 0,
DMACH_XD1,
DMACH_SDI,
DMACH_SPI0,
DMACH_SPI1,
DMACH_UART0,
DMACH_UART1,
DMACH_UART2,
DMACH_TIMER,
DMACH_I2S_IN,
DMACH_I2S_OUT,
DMACH_PCM_IN,
DMACH_PCM_OUT,
DMACH_MIC_IN,
DMACH_USB_EP1,
DMACH_USB_EP2,
DMACH_USB_EP3,
DMACH_USB_EP4,
DMACH_UART0_SRC2, /* s3c2412 second uart sources */
DMACH_UART1_SRC2,
DMACH_UART2_SRC2,
DMACH_UART3, /* s3c2443 has extra uart */
DMACH_UART3_SRC2,
DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */
DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */
DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */
DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */
DMACH_MAX, /* the end entry */
};
#endif /* __ASM_ARCH_DMA_H */
arch/arm/mach-s3c/fb-core-s3c24xx.h deleted 100644 → 0
View file @ 1027b4df
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2010 Samsung Electronics Co., Ltd.
* Pawel Osciak <p.osciak@samsung.com>
*
* Samsung framebuffer driver core functions
*/
#ifndef __ASM_PLAT_FB_CORE_S3C24XX_H
#define __ASM_PLAT_FB_CORE_S3C24XX_H __FILE__
/*
* These functions are only for use with the core support code, such as
* the CPU-specific initialization code.
*/
/* Re-define device name depending on support. */
static inline void s3c_fb_setname(char *name)
{
#ifdef CONFIG_S3C_DEV_FB
s3c_device_fb.name = name;
#endif
}
#endif /* __ASM_PLAT_FB_CORE_S3C24XX_H */
arch/arm/mach-s3c/gpio-samsung-s3c24xx.h deleted 100644 → 0
View file @ 1027b4df
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - GPIO lib support
*/
/* some boards require extra gpio capacity to support external
* devices that need GPIO.
*/
#ifndef GPIO_SAMSUNG_S3C24XX_H
#define GPIO_SAMSUNG_S3C24XX_H
#include "map.h"
/*
* GPIO sizes for various SoCs:
*
* 2410 2412 2440 2443 2416
* 2442
* ---- ---- ---- ---- ----
* A 23 22 25 16 27
* B 11 11 11 11 11
* C 16 16 16 16 16
* D 16 16 16 16 16
* E 16 16 16 16 16
* F 8 8 8 8 8
* G 16 16 16 16 8
* H 11 11 11 15 15
* J -- -- 13 16 --
* K -- -- -- -- 16
* L -- -- -- 15 14
* M -- -- -- 2 2
*/
/* GPIO bank sizes */
#define S3C2410_GPIO_A_NR (32)
#define S3C2410_GPIO_B_NR (32)
#define S3C2410_GPIO_C_NR (32)
#define S3C2410_GPIO_D_NR (32)
#define S3C2410_GPIO_E_NR (32)
#define S3C2410_GPIO_F_NR (32)
#define S3C2410_GPIO_G_NR (32)
#define S3C2410_GPIO_H_NR (32)
#define S3C2410_GPIO_J_NR (32) /* technically 16. */
#define S3C2410_GPIO_K_NR (32) /* technically 16. */
#define S3C2410_GPIO_L_NR (32) /* technically 15. */
#define S3C2410_GPIO_M_NR (32) /* technically 2. */
#if CONFIG_S3C_GPIO_SPACE != 0
#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
#endif
#define S3C2410_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
#ifndef __ASSEMBLY__
enum s3c_gpio_number {
S3C2410_GPIO_A_START = 0,
S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
};
#endif /* __ASSEMBLY__ */
/* S3C2410 GPIO number definitions. */
#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr))
#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr))
#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr))
#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr))
#ifdef CONFIG_CPU_S3C244X
#define S3C_GPIO_END (S3C2410_GPJ(0) + 32)
#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
#define S3C_GPIO_END (S3C2410_GPM(0) + 32)
#else
#define S3C_GPIO_END (S3C2410_GPH(0) + 32)
#endif
#endif /* GPIO_SAMSUNG_S3C24XX_H */
arch/arm/mach-s3c/gta02.h deleted 100644 → 0
View file @ 1027b4df
/* SPDX-License-Identifier: GPL-2.0 */
/*
* GTA02 header
*/
#ifndef __MACH_S3C24XX_GTA02_H
#define __MACH_S3C24XX_GTA02_H __FILE__
#include "regs-gpio.h"
#define GTA02_GPIO_AUX_LED S3C2410_GPB(2)
#define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9)
#define GTA02_GPIO_AUX_KEY S3C2410_GPF(6)
#define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7)
#define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */
#define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */
#define GTA02_IRQ_PCF50633 IRQ_EINT9
#endif /* __MACH_S3C24XX_GTA02_H */
arch/arm/mach-s3c/h1940-bluetooth.c deleted 100644 → 0
View file @ 1027b4df
// SPDX-License-Identifier: GPL-1.0+
//
// Copyright (c) Arnaud Patard <arnaud.patard@rtp-net.org>
//
// S3C2410 bluetooth "driver"
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/rfkill.h>
#include "gpio-cfg.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
#include "h1940.h"
#define DRV_NAME "h1940-bt"
/* Bluetooth control */
static void h1940bt_enable(int on)
{
if (on) {
/* Power on the chip */
gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 1);
/* Reset the chip */
mdelay(10);
gpio_set_value(S3C2410_GPH(1), 1);
mdelay(10);
gpio_set_value(S3C2410_GPH(1), 0);
h1940_led_blink_set(NULL, GPIO_LED_BLINK, NULL, NULL);
}
else {
gpio_set_value(S3C2410_GPH(1), 1);
mdelay(10);
gpio_set_value(S3C2410_GPH(1), 0);
mdelay(10);
gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0);
h1940_led_blink_set(NULL, GPIO_LED_NO_BLINK_LOW, NULL, NULL);
}
}
static int h1940bt_set_block(void *data, bool blocked)
{
h1940bt_enable(!blocked);
return 0;
}
static const struct rfkill_ops h1940bt_rfkill_ops = {
.set_block = h1940bt_set_block,
};
static int h1940bt_probe(struct platform_device *pdev)
{
struct rfkill *rfk;
int ret = 0;
ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev));
if (ret) {
dev_err(&pdev->dev, "could not get GPH1\n");
return ret;
}
ret = gpio_request(H1940_LATCH_BLUETOOTH_POWER, dev_name(&pdev->dev));
if (ret) {
gpio_free(S3C2410_GPH(1));
dev_err(&pdev->dev, "could not get BT_POWER\n");
return ret;
}
/* Configures BT serial port GPIOs */
s3c_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
s3c_gpio_setpull(S3C2410_GPH(0), S3C_GPIO_PULL_NONE);
s3c_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
s3c_gpio_setpull(S3C2410_GPH(1), S3C_GPIO_PULL_NONE);
s3c_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
s3c_gpio_setpull(S3C2410_GPH(2), S3C_GPIO_PULL_NONE);
s3c_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
s3c_gpio_setpull(S3C2410_GPH(3), S3C_GPIO_PULL_NONE);
rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH,
&h1940bt_rfkill_ops, NULL);
if (!rfk) {
ret = -ENOMEM;
goto err_rfk_alloc;
}
ret = rfkill_register(rfk);
if (ret)
goto err_rfkill;
platform_set_drvdata(pdev, rfk);
return 0;
err_rfkill:
rfkill_destroy(rfk);
err_rfk_alloc:
return ret;
}
static int h1940bt_remove(struct platform_device *pdev)
{
struct rfkill *rfk = platform_get_drvdata(pdev);
platform_set_drvdata(pdev, NULL);
gpio_free(S3C2410_GPH(1));
if (rfk) {
rfkill_unregister(rfk);
rfkill_destroy(rfk);
}
rfk = NULL;
h1940bt_enable(0);
return 0;
}
static struct platform_driver h1940bt_driver = {
.driver = {
.name = DRV_NAME,
},
.probe = h1940bt_probe,
.remove = h1940bt_remove,
};
module_platform_driver(h1940bt_driver);
MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip");
MODULE_LICENSE("GPL");
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2006 Ben Dooks <ben-linux@fluff.org>
*
* Copyright (c) 2005 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* iPAQ H1940 series definitions
*/
#ifndef __MACH_S3C24XX_H1940_H
#define __MACH_S3C24XX_H1940_H __FILE__
#define H1940_SUSPEND_CHECKSUM (0x30003ff8)
#define H1940_SUSPEND_RESUMEAT (0x30081000)
#define H1940_SUSPEND_CHECK (0x30080000)
struct gpio_desc;
extern void h1940_pm_return(void);
extern int h1940_led_blink_set(struct gpio_desc *desc, int state,
unsigned long *delay_on,
unsigned long *delay_off);
#include <linux/gpio.h>
#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x))
/* SD layer latch */
#define H1940_LATCH_LCD_P0 H1940_LATCH_GPIO(0)
#define H1940_LATCH_LCD_P1 H1940_LATCH_GPIO(1)
#define H1940_LATCH_LCD_P2 H1940_LATCH_GPIO(2)
#define H1940_LATCH_LCD_P3 H1940_LATCH_GPIO(3)
#define H1940_LATCH_MAX1698_nSHUTDOWN H1940_LATCH_GPIO(4)
#define H1940_LATCH_LED_RED H1940_LATCH_GPIO(5)
#define H1940_LATCH_SDQ7 H1940_LATCH_GPIO(6)
#define H1940_LATCH_USB_DP H1940_LATCH_GPIO(7)
/* CPU layer latch */
#define H1940_LATCH_UDA_POWER H1940_LATCH_GPIO(8)
#define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9)
#define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10)
#define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11)
#define H1940_LATCH_SD_POWER H1940_LATCH_GPIO(12)
#define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13)
#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14)
#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15)
#endif /* __MACH_S3C24XX_H1940_H */
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - hardware
*/
#ifndef __ASM_ARCH_HARDWARE_S3C24XX_H
#define __ASM_ARCH_HARDWARE_S3C24XX_H
extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
#endif /* __ASM_ARCH_HARDWARE_S3C24XX_H */
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// SPDX-License-Identifier: GPL-2.0-only
#include <linux/stddef.h>
#include <linux/export.h>
#include <linux/spi/s3c24xx-fiq.h>
EXPORT_SYMBOL(s3c24xx_spi_fiq_rx);
EXPORT_SYMBOL(s3c24xx_spi_fiq_txrx);
EXPORT_SYMBOL(s3c24xx_spi_fiq_tx);
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// SPDX-License-Identifier: GPL-2.0
//
// Samsung's S3C2416 flattened device tree enabled machine
//
// Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
//
// based on mach-exynos/mach-exynos4-dt.c
//
// Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
// http://www.samsung.com
// Copyright (c) 2010-2011 Linaro Ltd.
// www.linaro.org
#include <linux/clocksource.h>
#include <linux/irqchip.h>
#include <linux/serial_s3c.h>
#include <asm/mach/arch.h>
#include "map.h"
#include "cpu.h"
#include "pm.h"
#include "s3c24xx.h"
static void __init s3c2416_dt_map_io(void)
{
s3c24xx_init_io(NULL, 0);
}
static void __init s3c2416_dt_machine_init(void)
{
s3c_pm_init();
}
static const char *const s3c2416_dt_compat[] __initconst = {
"samsung,s3c2416",
"samsung,s3c2450",
NULL
};
DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
/* Maintainer: Heiko Stuebner <heiko@sntech.de> */
.dt_compat = s3c2416_dt_compat,
.map_io = s3c2416_dt_map_io,
.init_irq = irqchip_init,
.init_machine = s3c2416_dt_machine_init,
MACHINE_END
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