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Commit 61c67bfa authored by Kavya Sree Kotagiri's avatar Kavya Sree Kotagiri Committed by Kishon Vijay Abraham I
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phy: ocelot-serdes: Add support for SERDES6G muxing 

Adding support for SERDES6G muxing required for QSGMII mode of operation.
Signed-off-by: default avatarKavya Sree Kotagiri <kavyasree.kotagiri@microchip.com>
Signed-off-by: default avatarQuentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: default avatarSteen Hegelund <Steen.Hegelund@microchip.com>
Co-developed-by: default avatarQuentin Schulz <quentin.schulz@bootlin.com>
Co-developed-by: default avatarSteen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent eeda879b
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Showing with 238 additions and 2 deletions
drivers/phy/mscc/phy-ocelot-serdes.c
View file @ 61c67bfa
...@@ -31,6 +31,238 @@ struct serdes_macro { ...@@ -31,6 +31,238 @@ struct serdes_macro {
struct serdes_ctrl *ctrl; struct serdes_ctrl *ctrl;
}; };
#define MCB_S6G_CFG_TIMEOUT 50
static int __serdes_write_mcb_s6g(struct regmap *regmap, u8 macro, u32 op)
{
unsigned int regval = 0;
regmap_write(regmap, HSIO_MCB_S6G_ADDR_CFG, op |
HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(BIT(macro)));
return regmap_read_poll_timeout(regmap, HSIO_MCB_S6G_ADDR_CFG, regval,
(regval & op) != op, 100,
MCB_S6G_CFG_TIMEOUT * 1000);
}
static int serdes_commit_mcb_s6g(struct regmap *regmap, u8 macro)
{
return __serdes_write_mcb_s6g(regmap, macro,
HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT);
}
static int serdes_update_mcb_s6g(struct regmap *regmap, u8 macro)
{
return __serdes_write_mcb_s6g(regmap, macro,
HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT);
}
static int serdes_init_s6g(struct regmap *regmap, u8 serdes, int mode)
{
u32 pll_fsm_ctrl_data;
u32 ob_ena1v_mode;
u32 des_bw_ana;
u32 ob_ena_cas;
u32 if_mode;
u32 ob_lev;
u32 qrate;
int ret;
if (mode == PHY_INTERFACE_MODE_QSGMII) {
pll_fsm_ctrl_data = 120;
ob_ena1v_mode = 0;
ob_ena_cas = 0;
des_bw_ana = 5;
ob_lev = 24;
if_mode = 3;
qrate = 0;
} else {
pll_fsm_ctrl_data = 60;
ob_ena1v_mode = 1;
ob_ena_cas = 2;
des_bw_ana = 3;
ob_lev = 48;
if_mode = 1;
qrate = 1;
}
ret = serdes_update_mcb_s6g(regmap, serdes);
if (ret)
return ret;
/* Test pattern */
regmap_update_bits(regmap, HSIO_S6G_COMMON_CFG,
HSIO_S6G_COMMON_CFG_SYS_RST, 0);
regmap_update_bits(regmap, HSIO_S6G_PLL_CFG,
HSIO_S6G_PLL_CFG_PLL_FSM_ENA, 0);
regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
HSIO_S6G_IB_CFG_IB_SIG_DET_ENA |
HSIO_S6G_IB_CFG_IB_REG_ENA |
HSIO_S6G_IB_CFG_IB_SAM_ENA |
HSIO_S6G_IB_CFG_IB_EQZ_ENA |
HSIO_S6G_IB_CFG_IB_CONCUR |
HSIO_S6G_IB_CFG_IB_CAL_ENA,
HSIO_S6G_IB_CFG_IB_SIG_DET_ENA |
HSIO_S6G_IB_CFG_IB_REG_ENA |
HSIO_S6G_IB_CFG_IB_SAM_ENA |
HSIO_S6G_IB_CFG_IB_EQZ_ENA |
HSIO_S6G_IB_CFG_IB_CONCUR);
regmap_update_bits(regmap, HSIO_S6G_IB_CFG1,
HSIO_S6G_IB_CFG1_IB_FRC_OFFSET |
HSIO_S6G_IB_CFG1_IB_FRC_LP |
HSIO_S6G_IB_CFG1_IB_FRC_MID |
HSIO_S6G_IB_CFG1_IB_FRC_HP |
HSIO_S6G_IB_CFG1_IB_FILT_OFFSET |
HSIO_S6G_IB_CFG1_IB_FILT_LP |
HSIO_S6G_IB_CFG1_IB_FILT_MID |
HSIO_S6G_IB_CFG1_IB_FILT_HP,
HSIO_S6G_IB_CFG1_IB_FILT_OFFSET |
HSIO_S6G_IB_CFG1_IB_FILT_HP |
HSIO_S6G_IB_CFG1_IB_FILT_LP |
HSIO_S6G_IB_CFG1_IB_FILT_MID);
regmap_update_bits(regmap, HSIO_S6G_IB_CFG2,
HSIO_S6G_IB_CFG2_IB_UREG_M,
HSIO_S6G_IB_CFG2_IB_UREG(4));
regmap_update_bits(regmap, HSIO_S6G_IB_CFG3,
HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M |
HSIO_S6G_IB_CFG3_IB_INI_LP_M |
HSIO_S6G_IB_CFG3_IB_INI_MID_M |
HSIO_S6G_IB_CFG3_IB_INI_HP_M,
HSIO_S6G_IB_CFG3_IB_INI_OFFSET(31) |
HSIO_S6G_IB_CFG3_IB_INI_LP(1) |
HSIO_S6G_IB_CFG3_IB_INI_MID(31) |
HSIO_S6G_IB_CFG3_IB_INI_HP(0));
regmap_update_bits(regmap, HSIO_S6G_MISC_CFG,
HSIO_S6G_MISC_CFG_LANE_RST,
HSIO_S6G_MISC_CFG_LANE_RST);
ret = serdes_commit_mcb_s6g(regmap, serdes);
if (ret)
return ret;
/* OB + DES + IB + SER CFG */
regmap_update_bits(regmap, HSIO_S6G_OB_CFG,
HSIO_S6G_OB_CFG_OB_IDLE |
HSIO_S6G_OB_CFG_OB_ENA1V_MODE |
HSIO_S6G_OB_CFG_OB_POST0_M |
HSIO_S6G_OB_CFG_OB_PREC_M,
(ob_ena1v_mode ? HSIO_S6G_OB_CFG_OB_ENA1V_MODE : 0) |
HSIO_S6G_OB_CFG_OB_POST0(0) |
HSIO_S6G_OB_CFG_OB_PREC(0));
regmap_update_bits(regmap, HSIO_S6G_OB_CFG1,
HSIO_S6G_OB_CFG1_OB_ENA_CAS_M |
HSIO_S6G_OB_CFG1_OB_LEV_M,
HSIO_S6G_OB_CFG1_OB_LEV(ob_lev) |
HSIO_S6G_OB_CFG1_OB_ENA_CAS(ob_ena_cas));
regmap_update_bits(regmap, HSIO_S6G_DES_CFG,
HSIO_S6G_DES_CFG_DES_PHS_CTRL_M |
HSIO_S6G_DES_CFG_DES_CPMD_SEL_M |
HSIO_S6G_DES_CFG_DES_BW_ANA_M,
HSIO_S6G_DES_CFG_DES_PHS_CTRL(2) |
HSIO_S6G_DES_CFG_DES_CPMD_SEL(0) |
HSIO_S6G_DES_CFG_DES_BW_ANA(des_bw_ana));
regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M |
HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M,
HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(0) |
HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(0));
regmap_update_bits(regmap, HSIO_S6G_IB_CFG1,
HSIO_S6G_IB_CFG1_IB_TSDET_M,
HSIO_S6G_IB_CFG1_IB_TSDET(16));
regmap_update_bits(regmap, HSIO_S6G_SER_CFG,
HSIO_S6G_SER_CFG_SER_ALISEL_M |
HSIO_S6G_SER_CFG_SER_ENALI,
HSIO_S6G_SER_CFG_SER_ALISEL(0));
regmap_update_bits(regmap, HSIO_S6G_PLL_CFG,
HSIO_S6G_PLL_CFG_PLL_DIV4 |
HSIO_S6G_PLL_CFG_PLL_ENA_ROT |
HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M |
HSIO_S6G_PLL_CFG_PLL_ROT_DIR |
HSIO_S6G_PLL_CFG_PLL_ROT_FRQ,
HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA
(pll_fsm_ctrl_data));
regmap_update_bits(regmap, HSIO_S6G_COMMON_CFG,
HSIO_S6G_COMMON_CFG_SYS_RST |
HSIO_S6G_COMMON_CFG_ENA_LANE |
HSIO_S6G_COMMON_CFG_PWD_RX |
HSIO_S6G_COMMON_CFG_PWD_TX |
HSIO_S6G_COMMON_CFG_HRATE |
HSIO_S6G_COMMON_CFG_QRATE |
HSIO_S6G_COMMON_CFG_ENA_ELOOP |
HSIO_S6G_COMMON_CFG_ENA_FLOOP |
HSIO_S6G_COMMON_CFG_IF_MODE_M,
HSIO_S6G_COMMON_CFG_SYS_RST |
HSIO_S6G_COMMON_CFG_ENA_LANE |
(qrate ? HSIO_S6G_COMMON_CFG_QRATE : 0) |
HSIO_S6G_COMMON_CFG_IF_MODE(if_mode));
regmap_update_bits(regmap, HSIO_S6G_MISC_CFG,
HSIO_S6G_MISC_CFG_LANE_RST |
HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA |
HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA |
HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA,
HSIO_S6G_MISC_CFG_LANE_RST |
HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA);
ret = serdes_commit_mcb_s6g(regmap, serdes);
if (ret)
return ret;
regmap_update_bits(regmap, HSIO_S6G_PLL_CFG,
HSIO_S6G_PLL_CFG_PLL_FSM_ENA,
HSIO_S6G_PLL_CFG_PLL_FSM_ENA);
ret = serdes_commit_mcb_s6g(regmap, serdes);
if (ret)
return ret;
/* Wait for PLL bringup */
msleep(20);
regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
HSIO_S6G_IB_CFG_IB_CAL_ENA,
HSIO_S6G_IB_CFG_IB_CAL_ENA);
regmap_update_bits(regmap, HSIO_S6G_MISC_CFG,
HSIO_S6G_MISC_CFG_LANE_RST, 0);
ret = serdes_commit_mcb_s6g(regmap, serdes);
if (ret)
return ret;
/* Wait for calibration */
msleep(60);
regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M |
HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M,
HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(0) |
HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(7));
regmap_update_bits(regmap, HSIO_S6G_IB_CFG1,
HSIO_S6G_IB_CFG1_IB_TSDET_M,
HSIO_S6G_IB_CFG1_IB_TSDET(3));
/* IB CFG */
return 0;
}
#define MCB_S1G_CFG_TIMEOUT 50 #define MCB_S1G_CFG_TIMEOUT 50
static int __serdes_write_mcb_s1g(struct regmap *regmap, u8 macro, u32 op) static int __serdes_write_mcb_s1g(struct regmap *regmap, u8 macro, u32 op)
...@@ -110,7 +342,7 @@ struct serdes_mux { ...@@ -110,7 +342,7 @@ struct serdes_mux {
u32 mux; u32 mux;
}; };
#define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \ #define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \
.idx = _idx, \ .idx = _idx, \
.port = _port, \ .port = _port, \
.mode = _mode, \ .mode = _mode, \
...@@ -191,8 +423,12 @@ static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode) ...@@ -191,8 +423,12 @@ static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)
if (macro->idx <= SERDES1G_MAX) if (macro->idx <= SERDES1G_MAX)
return serdes_init_s1g(macro->ctrl->regs, macro->idx); return serdes_init_s1g(macro->ctrl->regs, macro->idx);
else if (macro->idx <= SERDES6G_MAX)
return serdes_init_s6g(macro->ctrl->regs,
macro->idx - (SERDES1G_MAX + 1),
ocelot_serdes_muxes[i].submode);
/* SERDES6G and PCIe not supported yet */ /* PCIe not supported yet */
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
......
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