Commit 62582341 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Takashi Iwai

ALSA/ASoC: hda: move SPIB/DRMS functionality from ext layer

The SPIB and DRMS capabilities are orthogonal to the DSP enablement
and can be used whether the stream is coupled or not.

The existing code partitioning makes limited sense, the capabilities
are parsed at the sound/hda level but helpers are located in
sound/hda/ext.

This patch moves all the SPIB/DRMS functionality to the sound/hda
layer. This reduces the complexity of the sound/hda/ext layer which is
now limited to handling the multi-link extensions and stream
coupling/decoupling helpers.

Note that this is an iso-functionality code move and rename, the
HDaudio legacy driver would need additional changes to make use of
these capabilities.
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20221019162115.185917-11-pierre-louis.bossart@linux.intel.comSigned-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent f9002510
......@@ -495,6 +495,13 @@ static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr)
snd_hdac_chip_writeb(chip, reg, \
(snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
/* update register macro */
#define snd_hdac_updatel(addr, reg, mask, val) \
writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg)
#define snd_hdac_updatew(addr, reg, mask, val) \
writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg)
/*
* HD-audio stream
*/
......@@ -511,6 +518,13 @@ struct hdac_stream {
void __iomem *sd_addr; /* stream descriptor pointer */
void __iomem *spib_addr; /* software position in buffers stream pointer */
void __iomem *fifo_addr; /* software position Max fifos stream pointer */
void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */
u32 dpib; /* DMA position in buffer */
u32 lpib; /* Linear position in buffer */
u32 sd_int_sta_mask; /* stream int status mask */
/* pcm support */
......@@ -575,6 +589,18 @@ void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
struct snd_pcm_substream *substream);
void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip,
bool enable, int index);
int snd_hdac_stream_set_spib(struct hdac_bus *bus,
struct hdac_stream *azx_dev, u32 value);
int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
struct hdac_stream *azx_dev);
void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
bool enable, int index);
int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
struct hdac_stream *azx_dev, u32 value);
int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value);
/*
* macros for easy use
*/
......
......@@ -23,9 +23,6 @@ void snd_hdac_ext_bus_device_remove(struct hdac_bus *bus);
void snd_hdac_ext_bus_ppcap_enable(struct hdac_bus *chip, bool enable);
void snd_hdac_ext_bus_ppcap_int_enable(struct hdac_bus *chip, bool enable);
void snd_hdac_ext_stream_spbcap_enable(struct hdac_bus *chip,
bool enable, int index);
int snd_hdac_ext_bus_get_ml_capabilities(struct hdac_bus *bus);
struct hdac_ext_link *snd_hdac_ext_bus_get_hlink_by_addr(struct hdac_bus *bus, int addr);
struct hdac_ext_link *snd_hdac_ext_bus_get_hlink_by_name(struct hdac_bus *bus,
......@@ -43,11 +40,6 @@ enum hdac_ext_stream_type {
* @hstream: hdac_stream
* @pphc_addr: processing pipe host stream pointer
* @pplc_addr: processing pipe link stream pointer
* @spib_addr: software position in buffers stream pointer
* @fifo_addr: software position Max fifos stream pointer
* @dpibr_addr: DMA position in buffer resume pointer
* @dpib: DMA position in buffer
* @lpib: Linear position in buffer
* @decoupled: stream host and link is decoupled
* @link_locked: link is locked
* @link_prepared: link is prepared
......@@ -59,13 +51,6 @@ struct hdac_ext_stream {
void __iomem *pphc_addr;
void __iomem *pplc_addr;
void __iomem *spib_addr;
void __iomem *fifo_addr;
void __iomem *dpibr_addr;
u32 dpib;
u32 lpib;
bool decoupled:1;
bool link_locked:1;
bool link_prepared;
......@@ -90,16 +75,6 @@ void snd_hdac_ext_stream_decouple_locked(struct hdac_bus *bus,
void snd_hdac_ext_stream_decouple(struct hdac_bus *bus,
struct hdac_ext_stream *azx_dev, bool decouple);
int snd_hdac_ext_stream_set_spib(struct hdac_bus *bus,
struct hdac_ext_stream *hext_stream, u32 value);
int snd_hdac_ext_stream_get_spbmaxfifo(struct hdac_bus *bus,
struct hdac_ext_stream *hext_stream);
void snd_hdac_ext_stream_drsm_enable(struct hdac_bus *bus,
bool enable, int index);
int snd_hdac_ext_stream_set_dpibr(struct hdac_bus *bus,
struct hdac_ext_stream *hext_stream, u32 value);
int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *hext_stream, u32 value);
void snd_hdac_ext_stream_start(struct hdac_ext_stream *hext_stream);
void snd_hdac_ext_stream_clear(struct hdac_ext_stream *hext_stream);
void snd_hdac_ext_stream_reset(struct hdac_ext_stream *hext_stream);
......@@ -131,15 +106,6 @@ int snd_hdac_ext_bus_link_put(struct hdac_bus *bus, struct hdac_ext_link *hlink)
void snd_hdac_ext_bus_link_power(struct hdac_device *codec, bool enable);
/* update register macro */
#define snd_hdac_updatel(addr, reg, mask, val) \
writel(((readl(addr + reg) & ~(mask)) | (val)), \
addr + reg)
#define snd_hdac_updatew(addr, reg, mask, val) \
writew(((readw(addr + reg) & ~(mask)) | (val)), \
addr + reg)
#define snd_hdac_adsp_writeb(chip, reg, value) \
snd_hdac_reg_writeb(chip, (chip)->dsp_ba + (reg), value)
#define snd_hdac_adsp_readb(chip, reg) \
......
......@@ -39,20 +39,6 @@ static void snd_hdac_ext_stream_init(struct hdac_bus *bus,
AZX_PPLC_INTERVAL * idx;
}
if (bus->spbcap) {
hext_stream->spib_addr = bus->spbcap + AZX_SPB_BASE +
AZX_SPB_INTERVAL * idx +
AZX_SPB_SPIB;
hext_stream->fifo_addr = bus->spbcap + AZX_SPB_BASE +
AZX_SPB_INTERVAL * idx +
AZX_SPB_MAXFIFO;
}
if (bus->drsmcap)
hext_stream->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +
AZX_DRSM_INTERVAL * idx;
hext_stream->decoupled = false;
snd_hdac_stream_init(bus, &hext_stream->hstream, idx, direction, tag);
}
......@@ -381,128 +367,3 @@ void snd_hdac_ext_stream_release(struct hdac_ext_stream *hext_stream, int type)
}
EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_release);
/**
* snd_hdac_ext_stream_spbcap_enable - enable SPIB for a stream
* @bus: HD-audio core bus
* @enable: flag to enable/disable SPIB
* @index: stream index for which SPIB need to be enabled
*/
void snd_hdac_ext_stream_spbcap_enable(struct hdac_bus *bus,
bool enable, int index)
{
u32 mask = 0;
if (!bus->spbcap) {
dev_err(bus->dev, "Address of SPB capability is NULL\n");
return;
}
mask |= (1 << index);
if (enable)
snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);
else
snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);
}
EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_spbcap_enable);
/**
* snd_hdac_ext_stream_set_spib - sets the spib value of a stream
* @bus: HD-audio core bus
* @hext_stream: hdac_ext_stream
* @value: spib value to set
*/
int snd_hdac_ext_stream_set_spib(struct hdac_bus *bus,
struct hdac_ext_stream *hext_stream, u32 value)
{
if (!bus->spbcap) {
dev_err(bus->dev, "Address of SPB capability is NULL\n");
return -EINVAL;
}
writel(value, hext_stream->spib_addr);
return 0;
}
EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_set_spib);
/**
* snd_hdac_ext_stream_get_spbmaxfifo - gets the spib value of a stream
* @bus: HD-audio core bus
* @hext_stream: hdac_ext_stream
*
* Return maxfifo for the stream
*/
int snd_hdac_ext_stream_get_spbmaxfifo(struct hdac_bus *bus,
struct hdac_ext_stream *hext_stream)
{
if (!bus->spbcap) {
dev_err(bus->dev, "Address of SPB capability is NULL\n");
return -EINVAL;
}
return readl(hext_stream->fifo_addr);
}
EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_get_spbmaxfifo);
/**
* snd_hdac_ext_stream_drsm_enable - enable DMA resume for a stream
* @bus: HD-audio core bus
* @enable: flag to enable/disable DRSM
* @index: stream index for which DRSM need to be enabled
*/
void snd_hdac_ext_stream_drsm_enable(struct hdac_bus *bus,
bool enable, int index)
{
u32 mask = 0;
if (!bus->drsmcap) {
dev_err(bus->dev, "Address of DRSM capability is NULL\n");
return;
}
mask |= (1 << index);
if (enable)
snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);
else
snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
}
EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_drsm_enable);
/**
* snd_hdac_ext_stream_set_dpibr - sets the dpibr value of a stream
* @bus: HD-audio core bus
* @hext_stream: hdac_ext_stream
* @value: dpib value to set
*/
int snd_hdac_ext_stream_set_dpibr(struct hdac_bus *bus,
struct hdac_ext_stream *hext_stream, u32 value)
{
if (!bus->drsmcap) {
dev_err(bus->dev, "Address of DRSM capability is NULL\n");
return -EINVAL;
}
writel(value, hext_stream->dpibr_addr);
return 0;
}
EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_set_dpibr);
/**
* snd_hdac_ext_stream_set_lpib - sets the lpib value of a stream
* @hext_stream: hdac_ext_stream
* @value: lpib value to set
*/
int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *hext_stream, u32 value)
{
snd_hdac_stream_writel(&hext_stream->hstream, SD_LPIB, value);
return 0;
}
EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_set_lpib);
......@@ -103,6 +103,20 @@ void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
azx_dev->stream_tag = tag;
snd_hdac_dsp_lock_init(azx_dev);
list_add_tail(&azx_dev->list, &bus->stream_list);
if (bus->spbcap) {
azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE +
AZX_SPB_INTERVAL * idx +
AZX_SPB_SPIB;
azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE +
AZX_SPB_INTERVAL * idx +
AZX_SPB_MAXFIFO;
}
if (bus->drsmcap)
azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +
AZX_DRSM_INTERVAL * idx;
}
EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
......@@ -718,6 +732,128 @@ void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
}
EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
/**
* snd_hdac_stream_spbcap_enable - enable SPIB for a stream
* @bus: HD-audio core bus
* @enable: flag to enable/disable SPIB
* @index: stream index for which SPIB need to be enabled
*/
void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus,
bool enable, int index)
{
u32 mask = 0;
if (!bus->spbcap) {
dev_err(bus->dev, "Address of SPB capability is NULL\n");
return;
}
mask |= (1 << index);
if (enable)
snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);
else
snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);
}
EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable);
/**
* snd_hdac_stream_set_spib - sets the spib value of a stream
* @bus: HD-audio core bus
* @azx_dev: hdac_stream
* @value: spib value to set
*/
int snd_hdac_stream_set_spib(struct hdac_bus *bus,
struct hdac_stream *azx_dev, u32 value)
{
if (!bus->spbcap) {
dev_err(bus->dev, "Address of SPB capability is NULL\n");
return -EINVAL;
}
writel(value, azx_dev->spib_addr);
return 0;
}
EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib);
/**
* snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream
* @bus: HD-audio core bus
* @azx_dev: hdac_stream
*
* Return maxfifo for the stream
*/
int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
struct hdac_stream *azx_dev)
{
if (!bus->spbcap) {
dev_err(bus->dev, "Address of SPB capability is NULL\n");
return -EINVAL;
}
return readl(azx_dev->fifo_addr);
}
EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo);
/**
* snd_hdac_stream_drsm_enable - enable DMA resume for a stream
* @bus: HD-audio core bus
* @enable: flag to enable/disable DRSM
* @index: stream index for which DRSM need to be enabled
*/
void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
bool enable, int index)
{
u32 mask = 0;
if (!bus->drsmcap) {
dev_err(bus->dev, "Address of DRSM capability is NULL\n");
return;
}
mask |= (1 << index);
if (enable)
snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);
else
snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
}
EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable);
/**
* snd_hdac_stream_set_dpibr - sets the dpibr value of a stream
* @bus: HD-audio core bus
* @azx_dev: hdac_stream
* @value: dpib value to set
*/
int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
struct hdac_stream *azx_dev, u32 value)
{
if (!bus->drsmcap) {
dev_err(bus->dev, "Address of DRSM capability is NULL\n");
return -EINVAL;
}
writel(value, azx_dev->dpibr_addr);
return 0;
}
EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr);
/**
* snd_hdac_stream_set_lpib - sets the lpib value of a stream
* @azx_dev: hdac_stream
* @value: lpib value to set
*/
int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value)
{
snd_hdac_stream_writel(azx_dev, SD_LPIB, value);
return 0;
}
EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib);
#ifdef CONFIG_SND_HDA_DSP_LOADER
/**
* snd_hdac_dsp_prepare - prepare for DSP loading
......
......@@ -369,8 +369,8 @@ int avs_hda_load_basefw(struct avs_dev *adev, struct firmware *fw)
goto release_stream;
/* enable SPIB for hda stream */
snd_hdac_ext_stream_spbcap_enable(bus, true, hstream->index);
ret = snd_hdac_ext_stream_set_spib(bus, estream, fw->size);
snd_hdac_stream_spbcap_enable(bus, true, hstream->index);
ret = snd_hdac_stream_set_spib(bus, hstream, fw->size);
if (ret)
goto cleanup_resources;
......@@ -400,8 +400,8 @@ int avs_hda_load_basefw(struct avs_dev *adev, struct firmware *fw)
cleanup_resources:
/* disable SPIB for hda stream */
snd_hdac_ext_stream_spbcap_enable(bus, false, hstream->index);
snd_hdac_ext_stream_set_spib(bus, estream, 0);
snd_hdac_stream_spbcap_enable(bus, false, hstream->index);
snd_hdac_stream_set_spib(bus, hstream, 0);
snd_hdac_dsp_cleanup(hstream, &dmab);
release_stream:
......@@ -436,8 +436,8 @@ int avs_hda_load_library(struct avs_dev *adev, struct firmware *lib, u32 id)
goto release_stream;
/* enable SPIB for hda stream */
snd_hdac_ext_stream_spbcap_enable(bus, true, stream->index);
snd_hdac_ext_stream_set_spib(bus, estream, lib->size);
snd_hdac_stream_spbcap_enable(bus, true, stream->index);
snd_hdac_stream_set_spib(bus, stream, lib->size);
memcpy(dmab.area, lib->data, lib->size);
......@@ -451,8 +451,8 @@ int avs_hda_load_library(struct avs_dev *adev, struct firmware *lib, u32 id)
}
/* disable SPIB for hda stream */
snd_hdac_ext_stream_spbcap_enable(bus, false, stream->index);
snd_hdac_ext_stream_set_spib(bus, estream, 0);
snd_hdac_stream_spbcap_enable(bus, false, stream->index);
snd_hdac_stream_set_spib(bus, stream, 0);
snd_hdac_dsp_cleanup(stream, &dmab);
release_stream:
......
......@@ -53,17 +53,15 @@ static int skl_dsp_setup_spib(struct device *dev, unsigned int size,
struct hdac_bus *bus = dev_get_drvdata(dev);
struct hdac_stream *stream = snd_hdac_get_stream(bus,
SNDRV_PCM_STREAM_PLAYBACK, stream_tag);
struct hdac_ext_stream *estream;
if (!stream)
return -EINVAL;
estream = stream_to_hdac_ext_stream(stream);
/* enable/disable SPIB for this hdac stream */
snd_hdac_ext_stream_spbcap_enable(bus, enable, stream->index);
snd_hdac_stream_spbcap_enable(bus, enable, stream->index);
/* set the spib value */
snd_hdac_ext_stream_set_spib(bus, estream, size);
snd_hdac_stream_set_spib(bus, stream, size);
return 0;
}
......
......@@ -467,6 +467,7 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
struct skl_module_cfg *mconfig;
struct hdac_bus *bus = get_bus_ctx(substream);
struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
struct hdac_stream *hstream = hdac_stream(stream);
struct snd_soc_dapm_widget *w;
int ret;
......@@ -484,11 +485,9 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
* dpib & lpib position to resume before starting the
* DMA
*/
snd_hdac_ext_stream_drsm_enable(bus, true,
hdac_stream(stream)->index);
snd_hdac_ext_stream_set_dpibr(bus, stream,
stream->lpib);
snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
snd_hdac_stream_drsm_enable(bus, true, hstream->index);
snd_hdac_stream_set_dpibr(bus, hstream, hstream->lpib);
snd_hdac_stream_set_lpib(hstream, hstream->lpib);
}
fallthrough;
......@@ -520,13 +519,13 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
ret = skl_decoupled_trigger(substream, cmd);
if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
/* save the dpib and lpib positions */
stream->dpib = readl(bus->remap_addr +
hstream->dpib = readl(bus->remap_addr +
AZX_REG_VS_SDXDPIB_XBASE +
(AZX_REG_VS_SDXDPIB_XINTERVAL *
hdac_stream(stream)->index));
hstream->index));
hstream->lpib = snd_hdac_stream_get_pos_lpib(hstream);
stream->lpib = snd_hdac_stream_get_pos_lpib(
hdac_stream(stream));
snd_hdac_ext_stream_decouple(bus, stream, false);
}
break;
......
......@@ -142,7 +142,6 @@ int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream)
{
struct hdac_stream *hstream = substream->runtime->private_data;
struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
struct snd_pcm_runtime *runtime = substream->runtime;
ssize_t appl_pos, buf_size;
u32 spib;
......@@ -156,7 +155,7 @@ int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substrea
if (!spib)
spib = buf_size;
sof_io_write(sdev, hext_stream->spib_addr, spib);
sof_io_write(sdev, hstream->spib_addr, spib);
return 0;
}
......
......@@ -173,7 +173,7 @@ int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
enable << hstream->index);
/* set the SPIB value */
sof_io_write(sdev, hext_stream->spib_addr, size);
sof_io_write(sdev, hstream->spib_addr, size);
return 0;
}
......@@ -883,18 +883,19 @@ int hda_dsp_stream_init(struct snd_sof_dev *sdev)
SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
SOF_HDA_PPLC_INTERVAL * i;
hstream = &hext_stream->hstream;
/* do we support SPIB */
if (sdev->bar[HDA_DSP_SPIB_BAR]) {
hext_stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
hstream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
SOF_HDA_SPIB_SPIB;
hext_stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
hstream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
SOF_HDA_SPIB_MAXFIFO;
}
hstream = &hext_stream->hstream;
hstream->bus = bus;
hstream->sd_int_sta_mask = 1 << i;
hstream->index = i;
......@@ -939,18 +940,19 @@ int hda_dsp_stream_init(struct snd_sof_dev *sdev)
SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
SOF_HDA_PPLC_INTERVAL * i;
hstream = &hext_stream->hstream;
/* do we support SPIB */
if (sdev->bar[HDA_DSP_SPIB_BAR]) {
hext_stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
hstream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
SOF_HDA_SPIB_SPIB;
hext_stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
hstream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
SOF_HDA_SPIB_MAXFIFO;
}
hstream = &hext_stream->hstream;
hstream->bus = bus;
hstream->sd_int_sta_mask = 1 << i;
hstream->index = i;
......
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