Commit 6389aa73 authored by David S. Miller's avatar David S. Miller

Merge branch 'for-davem' of...

Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
parents 0dbaee3b 1d212aa9
...@@ -1080,6 +1080,12 @@ S: Supported ...@@ -1080,6 +1080,12 @@ S: Supported
F: Documentation/aoe/ F: Documentation/aoe/
F: drivers/block/aoe/ F: drivers/block/aoe/
ATHEROS ATH GENERIC UTILITIES
M: "Luis R. Rodriguez" <lrodriguez@atheros.com>
L: linux-wireless@vger.kernel.org
S: Supported
F: drivers/net/wireless/ath/*
ATHEROS ATH5K WIRELESS DRIVER ATHEROS ATH5K WIRELESS DRIVER
M: Jiri Slaby <jirislaby@gmail.com> M: Jiri Slaby <jirislaby@gmail.com>
M: Nick Kossifidis <mickflemm@gmail.com> M: Nick Kossifidis <mickflemm@gmail.com>
......
...@@ -104,11 +104,6 @@ enum ath_cipher { ...@@ -104,11 +104,6 @@ enum ath_cipher {
ATH_CIPHER_MIC = 127 ATH_CIPHER_MIC = 127
}; };
enum ath_drv_info {
AR7010_DEVICE = BIT(0),
AR9287_DEVICE = BIT(1),
};
/** /**
* struct ath_ops - Register read/write operations * struct ath_ops - Register read/write operations
* *
...@@ -131,6 +126,7 @@ struct ath_bus_ops { ...@@ -131,6 +126,7 @@ struct ath_bus_ops {
void (*read_cachesize)(struct ath_common *common, int *csz); void (*read_cachesize)(struct ath_common *common, int *csz);
bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
void (*bt_coex_prep)(struct ath_common *common); void (*bt_coex_prep)(struct ath_common *common);
void (*extn_synch_en)(struct ath_common *common);
}; };
struct ath_common { struct ath_common {
...@@ -152,7 +148,6 @@ struct ath_common { ...@@ -152,7 +148,6 @@ struct ath_common {
u8 rx_chainmask; u8 rx_chainmask;
u32 rx_bufsize; u32 rx_bufsize;
u32 driver_info;
u32 keymax; u32 keymax;
DECLARE_BITMAP(keymap, ATH_KEYMAX); DECLARE_BITMAP(keymap, ATH_KEYMAX);
...@@ -186,4 +181,112 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry); ...@@ -186,4 +181,112 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry);
void ath_hw_cycle_counters_update(struct ath_common *common); void ath_hw_cycle_counters_update(struct ath_common *common);
int32_t ath_hw_get_listen_time(struct ath_common *common); int32_t ath_hw_get_listen_time(struct ath_common *common);
extern __attribute__ ((format (printf, 3, 4))) int
ath_printk(const char *level, struct ath_common *common, const char *fmt, ...);
#define ath_emerg(common, fmt, ...) \
ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
#define ath_alert(common, fmt, ...) \
ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
#define ath_crit(common, fmt, ...) \
ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
#define ath_err(common, fmt, ...) \
ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
#define ath_warn(common, fmt, ...) \
ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
#define ath_notice(common, fmt, ...) \
ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
#define ath_info(common, fmt, ...) \
ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
/**
* enum ath_debug_level - atheros wireless debug level
*
* @ATH_DBG_RESET: reset processing
* @ATH_DBG_QUEUE: hardware queue management
* @ATH_DBG_EEPROM: eeprom processing
* @ATH_DBG_CALIBRATE: periodic calibration
* @ATH_DBG_INTERRUPT: interrupt processing
* @ATH_DBG_REGULATORY: regulatory processing
* @ATH_DBG_ANI: adaptive noise immunitive processing
* @ATH_DBG_XMIT: basic xmit operation
* @ATH_DBG_BEACON: beacon handling
* @ATH_DBG_CONFIG: configuration of the hardware
* @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
* @ATH_DBG_PS: power save processing
* @ATH_DBG_HWTIMER: hardware timer handling
* @ATH_DBG_BTCOEX: bluetooth coexistance
* @ATH_DBG_BSTUCK: stuck beacons
* @ATH_DBG_ANY: enable all debugging
*
* The debug level is used to control the amount and type of debugging output
* we want to see. Each driver has its own method for enabling debugging and
* modifying debug level states -- but this is typically done through a
* module parameter 'debug' along with a respective 'debug' debugfs file
* entry.
*/
enum ATH_DEBUG {
ATH_DBG_RESET = 0x00000001,
ATH_DBG_QUEUE = 0x00000002,
ATH_DBG_EEPROM = 0x00000004,
ATH_DBG_CALIBRATE = 0x00000008,
ATH_DBG_INTERRUPT = 0x00000010,
ATH_DBG_REGULATORY = 0x00000020,
ATH_DBG_ANI = 0x00000040,
ATH_DBG_XMIT = 0x00000080,
ATH_DBG_BEACON = 0x00000100,
ATH_DBG_CONFIG = 0x00000200,
ATH_DBG_FATAL = 0x00000400,
ATH_DBG_PS = 0x00000800,
ATH_DBG_HWTIMER = 0x00001000,
ATH_DBG_BTCOEX = 0x00002000,
ATH_DBG_WMI = 0x00004000,
ATH_DBG_BSTUCK = 0x00008000,
ATH_DBG_ANY = 0xffffffff
};
#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
#ifdef CONFIG_ATH_DEBUG
#define ath_dbg(common, dbg_mask, fmt, ...) \
({ \
int rtn; \
if ((common)->debug_mask & dbg_mask) \
rtn = ath_printk(KERN_DEBUG, common, fmt, \
##__VA_ARGS__); \
else \
rtn = 0; \
\
rtn; \
})
#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
#else
static inline __attribute__ ((format (printf, 3, 4))) int
ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
const char *fmt, ...)
{
return 0;
}
#define ATH_DBG_WARN(foo, arg...) do {} while (0)
#define ATH_DBG_WARN_ON_ONCE(foo) ({ \
int __ret_warn_once = !!(foo); \
unlikely(__ret_warn_once); \
})
#endif /* CONFIG_ATH_DEBUG */
/** Returns string describing opmode, or NULL if unknown mode. */
#ifdef CONFIG_ATH_DEBUG
const char *ath_opmode_to_string(enum nl80211_iftype opmode);
#else
static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
{
return "UNKNOWN";
}
#endif
#endif /* ATH_H */ #endif /* ATH_H */
...@@ -60,7 +60,6 @@ ...@@ -60,7 +60,6 @@
#include "reg.h" #include "reg.h"
#include "debug.h" #include "debug.h"
#include "ani.h" #include "ani.h"
#include "../debug.h"
static int modparam_nohwcrypt; static int modparam_nohwcrypt;
module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
...@@ -76,7 +75,6 @@ MODULE_AUTHOR("Nick Kossifidis"); ...@@ -76,7 +75,6 @@ MODULE_AUTHOR("Nick Kossifidis");
MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
MODULE_LICENSE("Dual BSD/GPL"); MODULE_LICENSE("Dual BSD/GPL");
MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
static int ath5k_init(struct ieee80211_hw *hw); static int ath5k_init(struct ieee80211_hw *hw);
static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
...@@ -1881,7 +1879,8 @@ ath5k_beacon_send(struct ath5k_softc *sc) ...@@ -1881,7 +1879,8 @@ ath5k_beacon_send(struct ath5k_softc *sc)
sc->bmisscount = 0; sc->bmisscount = 0;
} }
if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) { if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
sc->opmode == NL80211_IFTYPE_MESH_POINT) {
u64 tsf = ath5k_hw_get_tsf64(ah); u64 tsf = ath5k_hw_get_tsf64(ah);
u32 tsftu = TSF_TO_TU(tsf); u32 tsftu = TSF_TO_TU(tsf);
int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval; int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
...@@ -1913,8 +1912,9 @@ ath5k_beacon_send(struct ath5k_softc *sc) ...@@ -1913,8 +1912,9 @@ ath5k_beacon_send(struct ath5k_softc *sc)
/* NB: hw still stops DMA, so proceed */ /* NB: hw still stops DMA, so proceed */
} }
/* refresh the beacon for AP mode */ /* refresh the beacon for AP or MESH mode */
if (sc->opmode == NL80211_IFTYPE_AP) if (sc->opmode == NL80211_IFTYPE_AP ||
sc->opmode == NL80211_IFTYPE_MESH_POINT)
ath5k_beacon_update(sc->hw, vif); ath5k_beacon_update(sc->hw, vif);
ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
...@@ -2341,8 +2341,9 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops) ...@@ -2341,8 +2341,9 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
/* Initialize driver private data */ /* Initialize driver private data */
SET_IEEE80211_DEV(hw, sc->dev); SET_IEEE80211_DEV(hw, sc->dev);
hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
IEEE80211_HW_SIGNAL_DBM; IEEE80211_HW_SIGNAL_DBM |
IEEE80211_HW_REPORTS_TX_ACK_STATUS;
hw->wiphy->interface_modes = hw->wiphy->interface_modes =
BIT(NL80211_IFTYPE_AP) | BIT(NL80211_IFTYPE_AP) |
...@@ -2653,7 +2654,7 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, ...@@ -2653,7 +2654,7 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
bool skip_pcu) bool skip_pcu)
{ {
struct ath5k_hw *ah = sc->ah; struct ath5k_hw *ah = sc->ah;
int ret; int ret, ani_mode;
ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
...@@ -2661,9 +2662,17 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, ...@@ -2661,9 +2662,17 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
synchronize_irq(sc->irq); synchronize_irq(sc->irq);
stop_tasklets(sc); stop_tasklets(sc);
if (chan) { /* Save ani mode and disable ANI durring
ath5k_drain_tx_buffs(sc); * reset. If we don't we might get false
* PHY error interrupts. */
ani_mode = ah->ah_sc->ani_state.ani_mode;
ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
/* We are going to empty hw queues
* so we should also free any remaining
* tx buffers */
ath5k_drain_tx_buffs(sc);
if (chan) {
sc->curchan = chan; sc->curchan = chan;
sc->curband = &sc->sbands[chan->band]; sc->curband = &sc->sbands[chan->band];
} }
...@@ -2680,12 +2689,12 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, ...@@ -2680,12 +2689,12 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
goto err; goto err;
} }
ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode); ath5k_ani_init(ah, ani_mode);
ah->ah_cal_next_full = jiffies; ah->ah_cal_next_full = jiffies;
ah->ah_cal_next_ani = jiffies; ah->ah_cal_next_ani = jiffies;
ah->ah_cal_next_nf = jiffies; ah->ah_cal_next_nf = jiffies;
ewma_init(&ah->ah_beacon_rssi_avg, 1000, 8); ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
/* /*
* Change channels and update the h/w rate map if we're switching; * Change channels and update the h/w rate map if we're switching;
...@@ -2790,33 +2799,46 @@ ath5k_init(struct ieee80211_hw *hw) ...@@ -2790,33 +2799,46 @@ ath5k_init(struct ieee80211_hw *hw)
goto err_bhal; goto err_bhal;
} }
/* This order matches mac80211's queue priority, so we can /* 5211 and 5212 usually support 10 queues but we better rely on the
* directly use the mac80211 queue number without any mapping */ * capability information */
txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
if (IS_ERR(txq)) { /* This order matches mac80211's queue priority, so we can
ATH5K_ERR(sc, "can't setup xmit queue\n"); * directly use the mac80211 queue number without any mapping */
ret = PTR_ERR(txq); txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
goto err_queues; if (IS_ERR(txq)) {
} ATH5K_ERR(sc, "can't setup xmit queue\n");
txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); ret = PTR_ERR(txq);
if (IS_ERR(txq)) { goto err_queues;
ATH5K_ERR(sc, "can't setup xmit queue\n"); }
ret = PTR_ERR(txq); txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
goto err_queues; if (IS_ERR(txq)) {
} ATH5K_ERR(sc, "can't setup xmit queue\n");
txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); ret = PTR_ERR(txq);
if (IS_ERR(txq)) { goto err_queues;
ATH5K_ERR(sc, "can't setup xmit queue\n"); }
ret = PTR_ERR(txq); txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
goto err_queues; if (IS_ERR(txq)) {
} ATH5K_ERR(sc, "can't setup xmit queue\n");
txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); ret = PTR_ERR(txq);
if (IS_ERR(txq)) { goto err_queues;
ATH5K_ERR(sc, "can't setup xmit queue\n"); }
ret = PTR_ERR(txq); txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
goto err_queues; if (IS_ERR(txq)) {
ATH5K_ERR(sc, "can't setup xmit queue\n");
ret = PTR_ERR(txq);
goto err_queues;
}
hw->queues = 4;
} else {
/* older hardware (5210) can only support one data queue */
txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
if (IS_ERR(txq)) {
ATH5K_ERR(sc, "can't setup xmit queue\n");
ret = PTR_ERR(txq);
goto err_queues;
}
hw->queues = 1;
} }
hw->queues = 4;
tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
...@@ -2977,7 +2999,8 @@ static int ath5k_add_interface(struct ieee80211_hw *hw, ...@@ -2977,7 +2999,8 @@ static int ath5k_add_interface(struct ieee80211_hw *hw,
/* Assign the vap/adhoc to a beacon xmit slot. */ /* Assign the vap/adhoc to a beacon xmit slot. */
if ((avf->opmode == NL80211_IFTYPE_AP) || if ((avf->opmode == NL80211_IFTYPE_AP) ||
(avf->opmode == NL80211_IFTYPE_ADHOC)) { (avf->opmode == NL80211_IFTYPE_ADHOC) ||
(avf->opmode == NL80211_IFTYPE_MESH_POINT)) {
int slot; int slot;
WARN_ON(list_empty(&sc->bcbuf)); WARN_ON(list_empty(&sc->bcbuf));
...@@ -2996,7 +3019,7 @@ static int ath5k_add_interface(struct ieee80211_hw *hw, ...@@ -2996,7 +3019,7 @@ static int ath5k_add_interface(struct ieee80211_hw *hw,
sc->bslot[avf->bslot] = vif; sc->bslot[avf->bslot] = vif;
if (avf->opmode == NL80211_IFTYPE_AP) if (avf->opmode == NL80211_IFTYPE_AP)
sc->num_ap_vifs++; sc->num_ap_vifs++;
else else if (avf->opmode == NL80211_IFTYPE_ADHOC)
sc->num_adhoc_vifs++; sc->num_adhoc_vifs++;
} }
......
...@@ -60,7 +60,6 @@ ...@@ -60,7 +60,6 @@
#include "base.h" #include "base.h"
#include "debug.h" #include "debug.h"
#include "../debug.h"
static unsigned int ath5k_debug; static unsigned int ath5k_debug;
module_param_named(debug, ath5k_debug, uint, 0); module_param_named(debug, ath5k_debug, uint, 0);
......
...@@ -72,7 +72,7 @@ static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) ...@@ -72,7 +72,7 @@ static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
i--) i--)
udelay(100); udelay(100);
if (i) if (!i)
ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA, ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
"failed to stop RX DMA !\n"); "failed to stop RX DMA !\n");
......
...@@ -45,6 +45,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = { ...@@ -45,6 +45,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
{ PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
{ 0 } { 0 }
}; };
MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
/* return bus cachesize in 4B word units */ /* return bus cachesize in 4B word units */
static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
......
...@@ -2742,10 +2742,12 @@ ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, ...@@ -2742,10 +2742,12 @@ ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
/* Write PDADC values on hw */ /* Write PDADC values on hw */
static void static void
ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
u8 pdcurves, u8 *pdg_to_idx)
{ {
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
u8 *pdadc_out = ah->ah_txpower.txp_pd_table; u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
u8 pdcurves = ee->ee_pd_gains[ee_mode];
u32 reg; u32 reg;
u8 i; u8 i;
...@@ -2992,7 +2994,7 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah, ...@@ -2992,7 +2994,7 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
ee->ee_pd_gains[ee_mode]); ee->ee_pd_gains[ee_mode]);
/* Write settings on hw */ /* Write settings on hw */
ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); ath5k_setup_pwr_to_pdadc_table(ah, ee_mode);
/* Set txp.offset, note that table_min /* Set txp.offset, note that table_min
* can be negative */ * can be negative */
...@@ -3114,12 +3116,6 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, ...@@ -3114,12 +3116,6 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
return -EINVAL; return -EINVAL;
} }
/* Reset TX power values */
memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
ah->ah_txpower.txp_min_pwr = 0;
ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
/* Initialize TX power table */ /* Initialize TX power table */
switch (ah->ah_radio) { switch (ah->ah_radio) {
case AR5K_RF5110: case AR5K_RF5110:
...@@ -3146,11 +3142,24 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, ...@@ -3146,11 +3142,24 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
* so there is no need to recalculate the powertable, we 'll * so there is no need to recalculate the powertable, we 'll
* just use the cached one */ * just use the cached one */
if (!fast) { if (!fast) {
/* Reset TX power values */
memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
ah->ah_txpower.txp_min_pwr = 0;
ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
/* Calculate the powertable */
ret = ath5k_setup_channel_powertable(ah, channel, ret = ath5k_setup_channel_powertable(ah, channel,
ee_mode, type); ee_mode, type);
if (ret) if (ret)
return ret; return ret;
} /* Write cached table on hw */
} else if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
ath5k_setup_pwr_to_pdadc_table(ah, ee_mode);
else
ath5k_setup_pcdac_table(ah);
/* Limit max power if we have a CTL available */ /* Limit max power if we have a CTL available */
ath5k_get_max_ctl_power(ah, channel); ath5k_get_max_ctl_power(ah, channel);
......
...@@ -152,8 +152,8 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, ...@@ -152,8 +152,8 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
/* /*
* Get queue by type * Get queue by type
*/ */
/*5210 only has 2 queues*/ /* 5210 only has 2 queues */
if (ah->ah_version == AR5K_AR5210) { if (ah->ah_capabilities.cap_queues.q_tx_num == 2) {
switch (queue_type) { switch (queue_type) {
case AR5K_TX_QUEUE_DATA: case AR5K_TX_QUEUE_DATA:
queue = AR5K_TX_QUEUE_ID_NOQCU_DATA; queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
......
...@@ -35,10 +35,9 @@ static bool ath_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data) ...@@ -35,10 +35,9 @@ static bool ath_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
pdata = (struct ath9k_platform_data *) pdev->dev.platform_data; pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
ath_print(common, ATH_DBG_FATAL, ath_err(common,
"%s: flash read failed, offset %08x " "%s: flash read failed, offset %08x is out of range\n",
"is out of range\n", __func__, off);
__func__, off);
return false; return false;
} }
......
...@@ -135,8 +135,8 @@ static void ath9k_ani_restart(struct ath_hw *ah) ...@@ -135,8 +135,8 @@ static void ath9k_ani_restart(struct ath_hw *ah)
cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
} }
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base); "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base);
ENABLE_REGWRITE_BUFFER(ah); ENABLE_REGWRITE_BUFFER(ah);
...@@ -267,11 +267,11 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel) ...@@ -267,11 +267,11 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
aniState->noiseFloor = BEACON_RSSI(ah); aniState->noiseFloor = BEACON_RSSI(ah);
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
aniState->ofdmNoiseImmunityLevel, aniState->ofdmNoiseImmunityLevel,
immunityLevel, aniState->noiseFloor, immunityLevel, aniState->noiseFloor,
aniState->rssiThrLow, aniState->rssiThrHigh); aniState->rssiThrLow, aniState->rssiThrHigh);
aniState->ofdmNoiseImmunityLevel = immunityLevel; aniState->ofdmNoiseImmunityLevel = immunityLevel;
...@@ -334,11 +334,11 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel) ...@@ -334,11 +334,11 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
const struct ani_cck_level_entry *entry_cck; const struct ani_cck_level_entry *entry_cck;
aniState->noiseFloor = BEACON_RSSI(ah); aniState->noiseFloor = BEACON_RSSI(ah);
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
aniState->cckNoiseImmunityLevel, immunityLevel, aniState->cckNoiseImmunityLevel, immunityLevel,
aniState->noiseFloor, aniState->rssiThrLow, aniState->noiseFloor, aniState->rssiThrLow,
aniState->rssiThrHigh); aniState->rssiThrHigh);
if ((ah->opmode == NL80211_IFTYPE_STATION || if ((ah->opmode == NL80211_IFTYPE_STATION ||
ah->opmode == NL80211_IFTYPE_ADHOC) && ah->opmode == NL80211_IFTYPE_ADHOC) &&
...@@ -358,7 +358,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel) ...@@ -358,7 +358,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
entry_cck->fir_step_level); entry_cck->fir_step_level);
/* Skip MRC CCK for pre AR9003 families */ /* Skip MRC CCK for pre AR9003 families */
if (!AR_SREV_9300_20_OR_LATER(ah)) if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
return; return;
if (aniState->mrcCCKOff == entry_cck->mrc_cck_on) if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
...@@ -478,8 +478,8 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning) ...@@ -478,8 +478,8 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
if (ah->opmode != NL80211_IFTYPE_STATION if (ah->opmode != NL80211_IFTYPE_STATION
&& ah->opmode != NL80211_IFTYPE_ADHOC) { && ah->opmode != NL80211_IFTYPE_ADHOC) {
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"Reset ANI state opmode %u\n", ah->opmode); "Reset ANI state opmode %u\n", ah->opmode);
ah->stats.ast_ani_reset++; ah->stats.ast_ani_reset++;
if (ah->opmode == NL80211_IFTYPE_AP) { if (ah->opmode == NL80211_IFTYPE_AP) {
...@@ -584,16 +584,14 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) ...@@ -584,16 +584,14 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
ATH9K_ANI_OFDM_DEF_LEVEL || ATH9K_ANI_OFDM_DEF_LEVEL ||
aniState->cckNoiseImmunityLevel != aniState->cckNoiseImmunityLevel !=
ATH9K_ANI_CCK_DEF_LEVEL) { ATH9K_ANI_CCK_DEF_LEVEL) {
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"Restore defaults: opmode %u " "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
"chan %d Mhz/0x%x is_scanning=%d " ah->opmode,
"ofdm:%d cck:%d\n", chan->channel,
ah->opmode, chan->channelFlags,
chan->channel, is_scanning,
chan->channelFlags, aniState->ofdmNoiseImmunityLevel,
is_scanning, aniState->cckNoiseImmunityLevel);
aniState->ofdmNoiseImmunityLevel,
aniState->cckNoiseImmunityLevel);
ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL); ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL); ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
...@@ -602,16 +600,14 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) ...@@ -602,16 +600,14 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
/* /*
* restore historical levels for this channel * restore historical levels for this channel
*/ */
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"Restore history: opmode %u " "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
"chan %d Mhz/0x%x is_scanning=%d " ah->opmode,
"ofdm:%d cck:%d\n", chan->channel,
ah->opmode, chan->channelFlags,
chan->channel, is_scanning,
chan->channelFlags, aniState->ofdmNoiseImmunityLevel,
is_scanning, aniState->cckNoiseImmunityLevel);
aniState->ofdmNoiseImmunityLevel,
aniState->cckNoiseImmunityLevel);
ath9k_hw_set_ofdm_nil(ah, ath9k_hw_set_ofdm_nil(ah,
aniState->ofdmNoiseImmunityLevel); aniState->ofdmNoiseImmunityLevel);
...@@ -666,19 +662,17 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) ...@@ -666,19 +662,17 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {
if (phyCnt1 < ofdm_base) { if (phyCnt1 < ofdm_base) {
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"phyCnt1 0x%x, resetting " "phyCnt1 0x%x, resetting counter value to 0x%x\n",
"counter value to 0x%x\n", phyCnt1, ofdm_base);
phyCnt1, ofdm_base);
REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
REG_WRITE(ah, AR_PHY_ERR_MASK_1, REG_WRITE(ah, AR_PHY_ERR_MASK_1,
AR_PHY_ERR_OFDM_TIMING); AR_PHY_ERR_OFDM_TIMING);
} }
if (phyCnt2 < cck_base) { if (phyCnt2 < cck_base) {
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"phyCnt2 0x%x, resetting " "phyCnt2 0x%x, resetting counter value to 0x%x\n",
"counter value to 0x%x\n", phyCnt2, cck_base);
phyCnt2, cck_base);
REG_WRITE(ah, AR_PHY_ERR_2, cck_base); REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
REG_WRITE(ah, AR_PHY_ERR_MASK_2, REG_WRITE(ah, AR_PHY_ERR_MASK_2,
AR_PHY_ERR_CCK_TIMING); AR_PHY_ERR_CCK_TIMING);
...@@ -719,13 +713,12 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -719,13 +713,12 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
cckPhyErrRate = aniState->cckPhyErrCount * 1000 / cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
aniState->listenTime; aniState->listenTime;
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"listenTime=%d OFDM:%d errs=%d/s CCK:%d " "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
"errs=%d/s ofdm_turn=%d\n", aniState->listenTime,
aniState->listenTime, aniState->ofdmNoiseImmunityLevel,
aniState->ofdmNoiseImmunityLevel, ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
ofdmPhyErrRate, aniState->cckNoiseImmunityLevel, cckPhyErrRate, aniState->ofdmsTurn);
cckPhyErrRate, aniState->ofdmsTurn);
if (aniState->listenTime > 5 * ah->aniperiod) { if (aniState->listenTime > 5 * ah->aniperiod) {
if (ofdmPhyErrRate <= ah->config.ofdm_trig_low && if (ofdmPhyErrRate <= ah->config.ofdm_trig_low &&
...@@ -755,7 +748,7 @@ void ath9k_enable_mib_counters(struct ath_hw *ah) ...@@ -755,7 +748,7 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
{ {
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n"); ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n");
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
...@@ -777,7 +770,7 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah) ...@@ -777,7 +770,7 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
{ {
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n"); ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n");
REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
...@@ -852,7 +845,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah) ...@@ -852,7 +845,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
int i; int i;
ath_print(common, ATH_DBG_ANI, "Initialize ANI\n"); ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n");
if (use_new_ani(ah)) { if (use_new_ani(ah)) {
ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW; ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
......
This diff is collapsed.
...@@ -494,9 +494,9 @@ int ar9002_hw_rf_claim(struct ath_hw *ah) ...@@ -494,9 +494,9 @@ int ar9002_hw_rf_claim(struct ath_hw *ah)
case AR_RAD2122_SREV_MAJOR: case AR_RAD2122_SREV_MAJOR:
break; break;
default: default:
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, ath_err(ath9k_hw_common(ah),
"Radio Chip Rev 0x%02X not supported\n", "Radio Chip Rev 0x%02X not supported\n",
val & AR_RADIO_SREV_MAJOR); val & AR_RADIO_SREV_MAJOR);
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
......
...@@ -111,8 +111,8 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) ...@@ -111,8 +111,8 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
} }
if (isr & AR_ISR_RXORN) { if (isr & AR_ISR_RXORN) {
ath_print(common, ATH_DBG_INTERRUPT, ath_dbg(common, ATH_DBG_INTERRUPT,
"receive FIFO overrun interrupt\n"); "receive FIFO overrun interrupt\n");
} }
*masked |= mask2; *masked |= mask2;
...@@ -147,25 +147,25 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) ...@@ -147,25 +147,25 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
if (fatal_int) { if (fatal_int) {
if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
ath_print(common, ATH_DBG_ANY, ath_dbg(common, ATH_DBG_ANY,
"received PCI FATAL interrupt\n"); "received PCI FATAL interrupt\n");
} }
if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
ath_print(common, ATH_DBG_ANY, ath_dbg(common, ATH_DBG_ANY,
"received PCI PERR interrupt\n"); "received PCI PERR interrupt\n");
} }
*masked |= ATH9K_INT_FATAL; *masked |= ATH9K_INT_FATAL;
} }
if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
ath_print(common, ATH_DBG_INTERRUPT, ath_dbg(common, ATH_DBG_INTERRUPT,
"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
REG_WRITE(ah, AR_RC, 0); REG_WRITE(ah, AR_RC, 0);
*masked |= ATH9K_INT_FATAL; *masked |= ATH9K_INT_FATAL;
} }
if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
ath_print(common, ATH_DBG_INTERRUPT, ath_dbg(common, ATH_DBG_INTERRUPT,
"AR_INTR_SYNC_LOCAL_TIMEOUT\n"); "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
} }
REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
......
...@@ -78,6 +78,7 @@ ...@@ -78,6 +78,7 @@
#define AR9300_EEPROM_SIZE (16*1024) #define AR9300_EEPROM_SIZE (16*1024)
#define FIXED_CCA_THRESHOLD 15 #define FIXED_CCA_THRESHOLD 15
#define AR9300_BASE_ADDR_4K 0xfff
#define AR9300_BASE_ADDR 0x3ff #define AR9300_BASE_ADDR 0x3ff
#define AR9300_BASE_ADDR_512 0x1ff #define AR9300_BASE_ADDR_512 0x1ff
...@@ -342,4 +343,5 @@ struct ar9300_eeprom { ...@@ -342,4 +343,5 @@ struct ar9300_eeprom {
s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah); s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah); s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
#endif #endif
This diff is collapsed.
...@@ -182,8 +182,8 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) ...@@ -182,8 +182,8 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
} }
if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
ath_print(common, ATH_DBG_INTERRUPT, ath_dbg(common, ATH_DBG_INTERRUPT,
"AR_INTR_SYNC_LOCAL_TIMEOUT\n"); "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
...@@ -249,8 +249,8 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, ...@@ -249,8 +249,8 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
(MS(ads->ds_info, AR_TxRxDesc) != 1)) { (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
"Tx Descriptor error %x\n", ads->ds_info); "Tx Descriptor error %x\n", ads->ds_info);
memset(ads, 0, sizeof(*ads)); memset(ads, 0, sizeof(*ads));
return -EIO; return -EIO;
} }
...@@ -658,10 +658,10 @@ void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah) ...@@ -658,10 +658,10 @@ void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
memset((void *) ah->ts_ring, 0, memset((void *) ah->ts_ring, 0,
ah->ts_size * sizeof(struct ar9003_txs)); ah->ts_size * sizeof(struct ar9003_txs));
ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
"TS Start 0x%x End 0x%x Virt %p, Size %d\n", "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
ah->ts_paddr_start, ah->ts_paddr_end, ah->ts_paddr_start, ah->ts_paddr_end,
ah->ts_ring, ah->ts_size); ah->ts_ring, ah->ts_size);
REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
......
...@@ -21,10 +21,12 @@ void ar9003_paprd_enable(struct ath_hw *ah, bool val) ...@@ -21,10 +21,12 @@ void ar9003_paprd_enable(struct ath_hw *ah, bool val)
{ {
REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0, REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1, if (ah->caps.tx_chainmask & BIT(1))
AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2, AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); if (ah->caps.tx_chainmask & BIT(2))
REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
} }
EXPORT_SYMBOL(ar9003_paprd_enable); EXPORT_SYMBOL(ar9003_paprd_enable);
...@@ -57,7 +59,8 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah) ...@@ -57,7 +59,8 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask); REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask);
REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask); REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask);
for (i = 0; i < 3; i++) {
for (i = 0; i < ah->caps.max_txchains; i++) {
REG_RMW_FIELD(ah, ctrl0[i], REG_RMW_FIELD(ah, ctrl0[i],
AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK, 1); AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK, 1);
REG_RMW_FIELD(ah, ctrl1[i], REG_RMW_FIELD(ah, ctrl1[i],
...@@ -102,8 +105,14 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah) ...@@ -102,8 +105,14 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, if (AR_SREV_9485(ah))
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -6); REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
-3);
else
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
-6);
REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,
-15); -15);
...@@ -620,13 +629,15 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah, ...@@ -620,13 +629,15 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah,
AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
training_power); training_power);
REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1, if (ah->caps.tx_chainmask & BIT(1))
AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1,
training_power); AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
training_power);
REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2, if (ah->caps.tx_chainmask & BIT(2))
AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2,
training_power); AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
training_power);
} }
EXPORT_SYMBOL(ar9003_paprd_populate_single_table); EXPORT_SYMBOL(ar9003_paprd_populate_single_table);
......
This diff is collapsed.
...@@ -260,7 +260,13 @@ ...@@ -260,7 +260,13 @@
#define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c) #define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c)
#define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20) #define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20)
#define AR_PHY_RESTART (AR_AGC_BASE + 0x24) #define AR_PHY_RESTART (AR_AGC_BASE + 0x24)
#define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28) #define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28)
#define AR_ANT_DIV_CTRL_ALL 0x7e000000
#define AR_ANT_DIV_CTRL_ALL_S 25
#define AR_ANT_DIV_ENABLE 0x1000000
#define AR_ANT_DIV_ENABLE_S 24
#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c) #define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30) #define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
#define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34) #define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34)
...@@ -271,7 +277,11 @@ ...@@ -271,7 +277,11 @@
#define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48) #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
#define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180) #define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180)
#define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184) #define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184)
#define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0) #define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0)
#define AR_FAST_DIV_ENABLE 0x2000
#define AR_FAST_DIV_ENABLE_S 13
#define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4) #define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4)
#define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8) #define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8)
...@@ -536,10 +546,18 @@ ...@@ -536,10 +546,18 @@
#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300) #define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
#define AR_PHY_TX_IQCAL_START_9485 (AR_SM_BASE + 0x3c4)
#define AR_PHY_TX_IQCAL_START_DO_CAL_9485 0x80000000
#define AR_PHY_TX_IQCAL_START_DO_CAL_9485_S 31
#define AR_PHY_TX_IQCAL_CONTROL_1_9485 (AR_SM_BASE + 0x3c8)
#define AR_PHY_TX_IQCAL_STATUS_B0_9485 (AR_SM_BASE + 0x3f0)
#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448) #define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448)
#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440) #define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440)
#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c) #define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c)
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 (AR_SM_BASE + 0x450) #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \
(AR_SREV_9485(ah) ? \
0x3d0 : 0x450) + ((_i) << 2))
#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0) #define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4) #define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
...@@ -568,7 +586,7 @@ ...@@ -568,7 +586,7 @@
#define AR_PHY_65NM_CH0_BIAS2 0x160c4 #define AR_PHY_65NM_CH0_BIAS2 0x160c4
#define AR_PHY_65NM_CH0_BIAS4 0x160cc #define AR_PHY_65NM_CH0_BIAS4 0x160cc
#define AR_PHY_65NM_CH0_RXTX4 0x1610c #define AR_PHY_65NM_CH0_RXTX4 0x1610c
#define AR_PHY_65NM_CH0_THERM 0x16290 #define AR_PHY_65NM_CH0_THERM (AR_SREV_9485(ah) ? 0x1628c : 0x16290)
#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
...@@ -584,6 +602,24 @@ ...@@ -584,6 +602,24 @@
#define AR_PHY_65NM_CH2_RXTX1 0x16900 #define AR_PHY_65NM_CH2_RXTX1 0x16900
#define AR_PHY_65NM_CH2_RXTX2 0x16904 #define AR_PHY_65NM_CH2_RXTX2 0x16904
#define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
#define AR_CH0_TOP2_XPABIASLVL 0xf000
#define AR_CH0_TOP2_XPABIASLVL_S 12
#define AR_CH0_XTAL (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
#define AR_CH0_XTAL_CAPINDAC 0x7f000000
#define AR_CH0_XTAL_CAPINDAC_S 24
#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
#define AR_CH0_XTAL_CAPOUTDAC_S 17
#define AR_PHY_PMU1 0x16c40
#define AR_PHY_PMU1_PWD 0x1
#define AR_PHY_PMU1_PWD_S 0
#define AR_PHY_PMU2 0x16c44
#define AR_PHY_PMU2_PGM 0x00200000
#define AR_PHY_PMU2_PGM_S 21
#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
...@@ -683,6 +719,7 @@ ...@@ -683,6 +719,7 @@
#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
#define AR_PHY_TXGAIN_FORCE 0x00000001 #define AR_PHY_TXGAIN_FORCE 0x00000001
#define AR_PHY_TXGAIN_FORCE_S 0
#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00 #define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000 #define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
...@@ -725,8 +762,13 @@ ...@@ -725,8 +762,13 @@
#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0 #define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff #define AR_PHY_CALIBRATED_GAINS_0 0x3e
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0 #define AR_PHY_CALIBRATED_GAINS_0_S 1
#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff
#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x0fffc000
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 14
#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
...@@ -785,7 +827,7 @@ ...@@ -785,7 +827,7 @@
#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220) #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
#define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240) #define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240)
#define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c) #define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 (AR_SM1_BASE + 0x450) #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM_BASE + 0x450 + ((_i) << 2))
/* /*
* Channel 2 Register Map * Channel 2 Register Map
...@@ -838,7 +880,7 @@ ...@@ -838,7 +880,7 @@
#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220) #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
#define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240) #define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240)
#define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c) #define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c)
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 (AR_SM2_BASE + 0x450) #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) (AR_SM2_BASE + 0x450 + ((_i) << 2))
#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
...@@ -945,7 +987,9 @@ ...@@ -945,7 +987,9 @@
#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000
#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17
#define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + 0x490) #define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + \
(AR_SREV_9485(ah) ? \
0x580 : 0x490))
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e
...@@ -961,11 +1005,15 @@ ...@@ -961,11 +1005,15 @@
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12
#define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + 0x494) #define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + \
(AR_SREV_9485(ah) ? \
0x584 : 0x494))
#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF
#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0
#define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + 0x498) #define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + \
(AR_SREV_9485(ah) ? \
0x588 : 0x498))
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0
...@@ -981,7 +1029,9 @@ ...@@ -981,7 +1029,9 @@
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29
#define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + 0x49c) #define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + \
(AR_SREV_9485(ah) ? \
0x58c : 0x49c))
#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000
#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000
......
This diff is collapsed.
...@@ -311,7 +311,7 @@ void ath_rx_cleanup(struct ath_softc *sc); ...@@ -311,7 +311,7 @@ void ath_rx_cleanup(struct ath_softc *sc);
int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
void ath_draintxq(struct ath_softc *sc, void ath_draintxq(struct ath_softc *sc,
struct ath_txq *txq, bool retry_tx); struct ath_txq *txq, bool retry_tx);
void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
......
...@@ -46,8 +46,8 @@ int ath_beaconq_config(struct ath_softc *sc) ...@@ -46,8 +46,8 @@ int ath_beaconq_config(struct ath_softc *sc)
} }
if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) { if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
ath_print(common, ATH_DBG_FATAL, ath_err(common,
"Unable to update h/w beacon queue parameters\n"); "Unable to update h/w beacon queue parameters\n");
return 0; return 0;
} else { } else {
ath9k_hw_resettxqueue(ah, sc->beacon.beaconq); ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
...@@ -120,11 +120,11 @@ static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) ...@@ -120,11 +120,11 @@ static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
memset(&txctl, 0, sizeof(struct ath_tx_control)); memset(&txctl, 0, sizeof(struct ath_tx_control));
txctl.txq = sc->beacon.cabq; txctl.txq = sc->beacon.cabq;
ath_print(common, ATH_DBG_XMIT, ath_dbg(common, ATH_DBG_XMIT,
"transmitting CABQ packet, skb: %p\n", skb); "transmitting CABQ packet, skb: %p\n", skb);
if (ath_tx_start(hw, skb, &txctl) != 0) { if (ath_tx_start(hw, skb, &txctl) != 0) {
ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n"); ath_dbg(common, ATH_DBG_XMIT, "CABQ TX failed\n");
dev_kfree_skb_any(skb); dev_kfree_skb_any(skb);
} }
} }
...@@ -189,8 +189,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, ...@@ -189,8 +189,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
dev_kfree_skb_any(skb); dev_kfree_skb_any(skb);
bf->bf_mpdu = NULL; bf->bf_mpdu = NULL;
bf->bf_buf_addr = 0; bf->bf_buf_addr = 0;
ath_print(common, ATH_DBG_FATAL, ath_err(common, "dma_mapping_error on beaconing\n");
"dma_mapping_error on beaconing\n");
return NULL; return NULL;
} }
...@@ -210,8 +209,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, ...@@ -210,8 +209,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
if (skb && cabq_depth) { if (skb && cabq_depth) {
if (sc->nvifs > 1) { if (sc->nvifs > 1) {
ath_print(common, ATH_DBG_BEACON, ath_dbg(common, ATH_DBG_BEACON,
"Flushing previous cabq traffic\n"); "Flushing previous cabq traffic\n");
ath_draintxq(sc, cabq, false); ath_draintxq(sc, cabq, false);
} }
} }
...@@ -283,7 +282,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) ...@@ -283,7 +282,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
/* NB: the beacon data buffer must be 32-bit aligned. */ /* NB: the beacon data buffer must be 32-bit aligned. */
skb = ieee80211_beacon_get(sc->hw, vif); skb = ieee80211_beacon_get(sc->hw, vif);
if (skb == NULL) { if (skb == NULL) {
ath_print(common, ATH_DBG_BEACON, "cannot get skb\n"); ath_dbg(common, ATH_DBG_BEACON, "cannot get skb\n");
return -ENOMEM; return -ENOMEM;
} }
...@@ -307,10 +306,9 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) ...@@ -307,10 +306,9 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
tsfadjust = intval * avp->av_bslot / ATH_BCBUF; tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
ath_print(common, ATH_DBG_BEACON, ath_dbg(common, ATH_DBG_BEACON,
"stagger beacons, bslot %d intval " "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
"%u tsfadjust %llu\n", avp->av_bslot, intval, (unsigned long long)tsfadjust);
avp->av_bslot, intval, (unsigned long long)tsfadjust);
((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
avp->tsf_adjust; avp->tsf_adjust;
...@@ -324,8 +322,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) ...@@ -324,8 +322,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
dev_kfree_skb_any(skb); dev_kfree_skb_any(skb);
bf->bf_mpdu = NULL; bf->bf_mpdu = NULL;
bf->bf_buf_addr = 0; bf->bf_buf_addr = 0;
ath_print(common, ATH_DBG_FATAL, ath_err(common, "dma_mapping_error on beacon alloc\n");
"dma_mapping_error on beacon alloc\n");
return -ENOMEM; return -ENOMEM;
} }
...@@ -382,13 +379,13 @@ void ath_beacon_tasklet(unsigned long data) ...@@ -382,13 +379,13 @@ void ath_beacon_tasklet(unsigned long data)
sc->beacon.bmisscnt++; sc->beacon.bmisscnt++;
if (sc->beacon.bmisscnt < BSTUCK_THRESH) { if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
ath_print(common, ATH_DBG_BSTUCK, ath_dbg(common, ATH_DBG_BSTUCK,
"missed %u consecutive beacons\n", "missed %u consecutive beacons\n",
sc->beacon.bmisscnt); sc->beacon.bmisscnt);
ath9k_hw_bstuck_nfcal(ah); ath9k_hw_bstuck_nfcal(ah);
} else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
ath_print(common, ATH_DBG_BSTUCK, ath_dbg(common, ATH_DBG_BSTUCK,
"beacon is officially stuck\n"); "beacon is officially stuck\n");
sc->sc_flags |= SC_OP_TSF_RESET; sc->sc_flags |= SC_OP_TSF_RESET;
ath_reset(sc, true); ath_reset(sc, true);
} }
...@@ -397,9 +394,9 @@ void ath_beacon_tasklet(unsigned long data) ...@@ -397,9 +394,9 @@ void ath_beacon_tasklet(unsigned long data)
} }
if (sc->beacon.bmisscnt != 0) { if (sc->beacon.bmisscnt != 0) {
ath_print(common, ATH_DBG_BSTUCK, ath_dbg(common, ATH_DBG_BSTUCK,
"resume beacon xmit after %u misses\n", "resume beacon xmit after %u misses\n",
sc->beacon.bmisscnt); sc->beacon.bmisscnt);
sc->beacon.bmisscnt = 0; sc->beacon.bmisscnt = 0;
} }
...@@ -425,9 +422,9 @@ void ath_beacon_tasklet(unsigned long data) ...@@ -425,9 +422,9 @@ void ath_beacon_tasklet(unsigned long data)
vif = sc->beacon.bslot[slot]; vif = sc->beacon.bslot[slot];
aphy = sc->beacon.bslot_aphy[slot]; aphy = sc->beacon.bslot_aphy[slot];
ath_print(common, ATH_DBG_BEACON, ath_dbg(common, ATH_DBG_BEACON,
"slot %d [tsf %llu tsftu %u intval %u] vif %p\n", "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
slot, tsf, tsftu, intval, vif); slot, tsf, tsftu, intval, vif);
bfaddr = 0; bfaddr = 0;
if (vif) { if (vif) {
...@@ -469,8 +466,8 @@ void ath_beacon_tasklet(unsigned long data) ...@@ -469,8 +466,8 @@ void ath_beacon_tasklet(unsigned long data)
* are still pending on the queue. * are still pending on the queue.
*/ */
if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) { if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
ath_print(common, ATH_DBG_FATAL, ath_err(common, "beacon queue %u did not stop?\n",
"beacon queue %u did not stop?\n", sc->beacon.beaconq); sc->beacon.beaconq);
} }
/* NB: cabq traffic should already be queued and primed */ /* NB: cabq traffic should already be queued and primed */
...@@ -556,8 +553,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc, ...@@ -556,8 +553,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
/* No need to configure beacon if we are not associated */ /* No need to configure beacon if we are not associated */
if (!common->curaid) { if (!common->curaid) {
ath_print(common, ATH_DBG_BEACON, ath_dbg(common, ATH_DBG_BEACON,
"STA is not yet associated..skipping beacon config\n"); "STA is not yet associated..skipping beacon config\n");
return; return;
} }
...@@ -650,11 +647,11 @@ static void ath_beacon_config_sta(struct ath_softc *sc, ...@@ -650,11 +647,11 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
/* TSF out of range threshold fixed at 1 second */ /* TSF out of range threshold fixed at 1 second */
bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); ath_dbg(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
ath_print(common, ATH_DBG_BEACON, ath_dbg(common, ATH_DBG_BEACON,
"bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
bs.bs_bmissthreshold, bs.bs_sleepduration, bs.bs_bmissthreshold, bs.bs_sleepduration,
bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
/* Set the computed STA beacon timers */ /* Set the computed STA beacon timers */
...@@ -690,9 +687,9 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc, ...@@ -690,9 +687,9 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
nexttbtt += intval; nexttbtt += intval;
} while (nexttbtt < tsftu); } while (nexttbtt < tsftu);
ath_print(common, ATH_DBG_BEACON, ath_dbg(common, ATH_DBG_BEACON,
"IBSS nexttbtt %u intval %u (%u)\n", "IBSS nexttbtt %u intval %u (%u)\n",
nexttbtt, intval, conf->beacon_interval); nexttbtt, intval, conf->beacon_interval);
/* /*
* In IBSS mode enable the beacon timers but only enable SWBA interrupts * In IBSS mode enable the beacon timers but only enable SWBA interrupts
...@@ -755,8 +752,8 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif) ...@@ -755,8 +752,8 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
ath_beacon_config_sta(sc, cur_conf); ath_beacon_config_sta(sc, cur_conf);
break; break;
default: default:
ath_print(common, ATH_DBG_CONFIG, ath_dbg(common, ATH_DBG_CONFIG,
"Unsupported beaconing mode\n"); "Unsupported beaconing mode\n");
return; return;
} }
......
...@@ -97,12 +97,12 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah, ...@@ -97,12 +97,12 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
if (h[i].privNF > limit->max) { if (h[i].privNF > limit->max) {
high_nf_mid = true; high_nf_mid = true;
ath_print(common, ATH_DBG_CALIBRATE, ath_dbg(common, ATH_DBG_CALIBRATE,
"NFmid[%d] (%d) > MAX (%d), %s\n", "NFmid[%d] (%d) > MAX (%d), %s\n",
i, h[i].privNF, limit->max, i, h[i].privNF, limit->max,
(cal->nfcal_interference ? (cal->nfcal_interference ?
"not corrected (due to interference)" : "not corrected (due to interference)" :
"correcting to MAX")); "correcting to MAX"));
/* /*
* Normally we limit the average noise floor by the * Normally we limit the average noise floor by the
...@@ -180,18 +180,18 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) ...@@ -180,18 +180,18 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
return true; return true;
if (currCal->calState != CAL_DONE) { if (currCal->calState != CAL_DONE) {
ath_print(common, ATH_DBG_CALIBRATE, ath_dbg(common, ATH_DBG_CALIBRATE,
"Calibration state incorrect, %d\n", "Calibration state incorrect, %d\n",
currCal->calState); currCal->calState);
return true; return true;
} }
if (!(ah->supp_cals & currCal->calData->calType)) if (!(ah->supp_cals & currCal->calData->calType))
return true; return true;
ath_print(common, ATH_DBG_CALIBRATE, ath_dbg(common, ATH_DBG_CALIBRATE,
"Resetting Cal %d state for channel %u\n", "Resetting Cal %d state for channel %u\n",
currCal->calData->calType, conf->channel->center_freq); currCal->calData->calType, conf->channel->center_freq);
ah->caldata->CalValid &= ~currCal->calData->calType; ah->caldata->CalValid &= ~currCal->calData->calType;
currCal->calState = CAL_WAITING; currCal->calState = CAL_WAITING;
...@@ -279,9 +279,9 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -279,9 +279,9 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
* noisefloor until the next calibration timer. * noisefloor until the next calibration timer.
*/ */
if (j == 1000) { if (j == 1000) {
ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf " ath_dbg(common, ATH_DBG_ANY,
"to load: AR_PHY_AGC_CONTROL=0x%x\n", "Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
REG_READ(ah, AR_PHY_AGC_CONTROL)); REG_READ(ah, AR_PHY_AGC_CONTROL));
return; return;
} }
...@@ -318,19 +318,19 @@ static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf) ...@@ -318,19 +318,19 @@ static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
if (!nf[i]) if (!nf[i])
continue; continue;
ath_print(common, ATH_DBG_CALIBRATE, ath_dbg(common, ATH_DBG_CALIBRATE,
"NF calibrated [%s] [chain %d] is %d\n", "NF calibrated [%s] [chain %d] is %d\n",
(i >= 3 ? "ext" : "ctl"), i % 3, nf[i]); (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
if (nf[i] > ATH9K_NF_TOO_HIGH) { if (nf[i] > ATH9K_NF_TOO_HIGH) {
ath_print(common, ATH_DBG_CALIBRATE, ath_dbg(common, ATH_DBG_CALIBRATE,
"NF[%d] (%d) > MAX (%d), correcting to MAX", "NF[%d] (%d) > MAX (%d), correcting to MAX\n",
i, nf[i], ATH9K_NF_TOO_HIGH); i, nf[i], ATH9K_NF_TOO_HIGH);
nf[i] = limit->max; nf[i] = limit->max;
} else if (nf[i] < limit->min) { } else if (nf[i] < limit->min) {
ath_print(common, ATH_DBG_CALIBRATE, ath_dbg(common, ATH_DBG_CALIBRATE,
"NF[%d] (%d) < MIN (%d), correcting to NOM", "NF[%d] (%d) < MIN (%d), correcting to NOM\n",
i, nf[i], limit->min); i, nf[i], limit->min);
nf[i] = limit->nominal; nf[i] = limit->nominal;
} }
} }
...@@ -347,8 +347,8 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -347,8 +347,8 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
chan->channelFlags &= (~CHANNEL_CW_INT); chan->channelFlags &= (~CHANNEL_CW_INT);
if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
ath_print(common, ATH_DBG_CALIBRATE, ath_dbg(common, ATH_DBG_CALIBRATE,
"NF did not complete in calibration window\n"); "NF did not complete in calibration window\n");
return false; return false;
} }
...@@ -357,10 +357,9 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -357,10 +357,9 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
nf = nfarray[0]; nf = nfarray[0];
if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh) if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
&& nf > nfThresh) { && nf > nfThresh) {
ath_print(common, ATH_DBG_CALIBRATE, ath_dbg(common, ATH_DBG_CALIBRATE,
"noise floor failed detected; " "noise floor failed detected; detected %d, threshold %d\n",
"detected %d, threshold %d\n", nf, nfThresh);
nf, nfThresh);
chan->channelFlags |= CHANNEL_CW_INT; chan->channelFlags |= CHANNEL_CW_INT;
} }
......
...@@ -180,8 +180,8 @@ void ath9k_cmn_btcoex_bt_stomp(struct ath_common *common, ...@@ -180,8 +180,8 @@ void ath9k_cmn_btcoex_bt_stomp(struct ath_common *common,
AR_STOMP_NONE_WLAN_WGHT); AR_STOMP_NONE_WLAN_WGHT);
break; break;
default: default:
ath_print(common, ATH_DBG_BTCOEX, ath_dbg(common, ATH_DBG_BTCOEX,
"Invalid Stomptype\n"); "Invalid Stomptype\n");
break; break;
} }
......
...@@ -17,7 +17,6 @@ ...@@ -17,7 +17,6 @@
#include <net/mac80211.h> #include <net/mac80211.h>
#include "../ath.h" #include "../ath.h"
#include "../debug.h"
#include "hw.h" #include "hw.h"
#include "hw-ops.h" #include "hw-ops.h"
......
...@@ -273,8 +273,8 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah) ...@@ -273,8 +273,8 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
break; break;
default: default:
ath_print(common, ATH_DBG_EEPROM, ath_dbg(common, ATH_DBG_EEPROM,
"Invalid chainmask configuration\n"); "Invalid chainmask configuration\n");
break; break;
} }
} }
......
...@@ -37,14 +37,14 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) ...@@ -37,14 +37,14 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
eep_start_loc = 64; eep_start_loc = 64;
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
ath_print(common, ATH_DBG_EEPROM, ath_dbg(common, ATH_DBG_EEPROM,
"Reading from EEPROM, not flash\n"); "Reading from EEPROM, not flash\n");
} }
for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) { if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
ath_print(common, ATH_DBG_EEPROM, ath_dbg(common, ATH_DBG_EEPROM,
"Unable to read eeprom region\n"); "Unable to read eeprom region\n");
return false; return false;
} }
eep_data++; eep_data++;
...@@ -69,13 +69,12 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) ...@@ -69,13 +69,12 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
&magic)) { &magic)) {
ath_print(common, ATH_DBG_FATAL, ath_err(common, "Reading Magic # failed\n");
"Reading Magic # failed\n");
return false; return false;
} }
ath_print(common, ATH_DBG_EEPROM, ath_dbg(common, ATH_DBG_EEPROM,
"Read Magic = 0x%04X\n", magic); "Read Magic = 0x%04X\n", magic);
if (magic != AR5416_EEPROM_MAGIC) { if (magic != AR5416_EEPROM_MAGIC) {
magic2 = swab16(magic); magic2 = swab16(magic);
...@@ -90,16 +89,15 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) ...@@ -90,16 +89,15 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
eepdata++; eepdata++;
} }
} else { } else {
ath_print(common, ATH_DBG_FATAL, ath_err(common,
"Invalid EEPROM Magic. " "Invalid EEPROM Magic. Endianness mismatch.\n");
"endianness mismatch.\n");
return -EINVAL; return -EINVAL;
} }
} }
} }
ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
need_swap ? "True" : "False"); need_swap ? "True" : "False");
if (need_swap) if (need_swap)
el = swab16(ah->eeprom.map4k.baseEepHeader.length); el = swab16(ah->eeprom.map4k.baseEepHeader.length);
...@@ -120,8 +118,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) ...@@ -120,8 +118,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
u32 integer; u32 integer;
u16 word; u16 word;
ath_print(common, ATH_DBG_EEPROM, ath_dbg(common, ATH_DBG_EEPROM,
"EEPROM Endianness is not native.. Changing\n"); "EEPROM Endianness is not native.. Changing\n");
word = swab16(eep->baseEepHeader.length); word = swab16(eep->baseEepHeader.length);
eep->baseEepHeader.length = word; eep->baseEepHeader.length = word;
...@@ -163,9 +161,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) ...@@ -163,9 +161,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
ath_print(common, ATH_DBG_FATAL, ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
"Bad EEPROM checksum 0x%x or revision 0x%04x\n", sum, ah->eep_ops->get_eeprom_ver(ah));
sum, ah->eep_ops->get_eeprom_ver(ah));
return -EINVAL; return -EINVAL;
} }
...@@ -488,21 +485,20 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, ...@@ -488,21 +485,20 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
((pdadcValues[4 * j + 3] & 0xFF) << 24); ((pdadcValues[4 * j + 3] & 0xFF) << 24);
REG_WRITE(ah, regOffset, reg32); REG_WRITE(ah, regOffset, reg32);
ath_print(common, ATH_DBG_EEPROM, ath_dbg(common, ATH_DBG_EEPROM,
"PDADC (%d,%4x): %4.4x %8.8x\n", "PDADC (%d,%4x): %4.4x %8.8x\n",
i, regChainOffset, regOffset, i, regChainOffset, regOffset,
reg32); reg32);
ath_print(common, ATH_DBG_EEPROM, ath_dbg(common, ATH_DBG_EEPROM,
"PDADC: Chain %d | " "PDADC: Chain %d | "
"PDADC %3d Value %3d | " "PDADC %3d Value %3d | "
"PDADC %3d Value %3d | " "PDADC %3d Value %3d | "
"PDADC %3d Value %3d | " "PDADC %3d Value %3d | "
"PDADC %3d Value %3d |\n", "PDADC %3d Value %3d |\n",
i, 4 * j, pdadcValues[4 * j], i, 4 * j, pdadcValues[4 * j],
4 * j + 1, pdadcValues[4 * j + 1], 4 * j + 1, pdadcValues[4 * j + 1],
4 * j + 2, pdadcValues[4 * j + 2], 4 * j + 2, pdadcValues[4 * j + 2],
4 * j + 3, 4 * j + 3, pdadcValues[4 * j + 3]);
pdadcValues[4 * j + 3]);
regOffset += 4; regOffset += 4;
} }
...@@ -1181,17 +1177,17 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) ...@@ -1181,17 +1177,17 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
u16 spur_val = AR_NO_SPUR; u16 spur_val = AR_NO_SPUR;
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"Getting spur idx %d is2Ghz. %d val %x\n", "Getting spur idx:%d is2Ghz:%d val:%x\n",
i, is2GHz, ah->config.spurchans[i][is2GHz]); i, is2GHz, ah->config.spurchans[i][is2GHz]);
switch (ah->config.spurmode) { switch (ah->config.spurmode) {
case SPUR_DISABLE: case SPUR_DISABLE:
break; break;
case SPUR_ENABLE_IOCTL: case SPUR_ENABLE_IOCTL:
spur_val = ah->config.spurchans[i][is2GHz]; spur_val = ah->config.spurchans[i][is2GHz];
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"Getting spur val from new loc. %d\n", spur_val); "Getting spur val from new loc. %d\n", spur_val);
break; break;
case SPUR_ENABLE_EEPROM: case SPUR_ENABLE_EEPROM:
spur_val = EEP_MAP4K_SPURCHAN; spur_val = EEP_MAP4K_SPURCHAN;
......
...@@ -37,21 +37,21 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah) ...@@ -37,21 +37,21 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
int addr, eep_start_loc; int addr, eep_start_loc;
eep_data = (u16 *)eep; eep_data = (u16 *)eep;
if (!common->driver_info) if (common->bus_ops->ath_bus_type == ATH_USB)
eep_start_loc = AR9287_EEP_START_LOC;
else
eep_start_loc = AR9287_HTC_EEP_START_LOC; eep_start_loc = AR9287_HTC_EEP_START_LOC;
else
eep_start_loc = AR9287_EEP_START_LOC;
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
ath_print(common, ATH_DBG_EEPROM, ath_dbg(common, ATH_DBG_EEPROM,
"Reading from EEPROM, not flash\n"); "Reading from EEPROM, not flash\n");
} }
for (addr = 0; addr < NUM_EEP_WORDS; addr++) { for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
eep_data)) { eep_data)) {
ath_print(common, ATH_DBG_EEPROM, ath_dbg(common, ATH_DBG_EEPROM,
"Unable to read eeprom region\n"); "Unable to read eeprom region\n");
return false; return false;
} }
eep_data++; eep_data++;
...@@ -72,13 +72,12 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) ...@@ -72,13 +72,12 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
&magic)) { &magic)) {
ath_print(common, ATH_DBG_FATAL, ath_err(common, "Reading Magic # failed\n");
"Reading Magic # failed\n");
return false; return false;
} }
ath_print(common, ATH_DBG_EEPROM, ath_dbg(common, ATH_DBG_EEPROM,
"Read Magic = 0x%04X\n", magic); "Read Magic = 0x%04X\n", magic);
if (magic != AR5416_EEPROM_MAGIC) { if (magic != AR5416_EEPROM_MAGIC) {
magic2 = swab16(magic); magic2 = swab16(magic);
...@@ -93,16 +92,15 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) ...@@ -93,16 +92,15 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
eepdata++; eepdata++;
} }
} else { } else {
ath_print(common, ATH_DBG_FATAL, ath_err(common,
"Invalid EEPROM Magic. " "Invalid EEPROM Magic. Endianness mismatch.\n");
"Endianness mismatch.\n");
return -EINVAL; return -EINVAL;
} }
} }
} }
ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
need_swap ? "True" : "False"); need_swap ? "True" : "False");
if (need_swap) if (need_swap)
el = swab16(ah->eeprom.map9287.baseEepHeader.length); el = swab16(ah->eeprom.map9287.baseEepHeader.length);
...@@ -160,9 +158,8 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) ...@@ -160,9 +158,8 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
|| ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
ath_print(common, ATH_DBG_FATAL, ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
"Bad EEPROM checksum 0x%x or revision 0x%04x\n", sum, ah->eep_ops->get_eeprom_ver(ah));
sum, ah->eep_ops->get_eeprom_ver(ah));
return -EINVAL; return -EINVAL;
} }
...@@ -1152,17 +1149,17 @@ static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah, ...@@ -1152,17 +1149,17 @@ static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
u16 spur_val = AR_NO_SPUR; u16 spur_val = AR_NO_SPUR;
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"Getting spur idx %d is2Ghz. %d val %x\n", "Getting spur idx:%d is2Ghz:%d val:%x\n",
i, is2GHz, ah->config.spurchans[i][is2GHz]); i, is2GHz, ah->config.spurchans[i][is2GHz]);
switch (ah->config.spurmode) { switch (ah->config.spurmode) {
case SPUR_DISABLE: case SPUR_DISABLE:
break; break;
case SPUR_ENABLE_IOCTL: case SPUR_ENABLE_IOCTL:
spur_val = ah->config.spurchans[i][is2GHz]; spur_val = ah->config.spurchans[i][is2GHz];
ath_print(common, ATH_DBG_ANI, ath_dbg(common, ATH_DBG_ANI,
"Getting spur val from new loc. %d\n", spur_val); "Getting spur val from new loc. %d\n", spur_val);
break; break;
case SPUR_ENABLE_EEPROM: case SPUR_ENABLE_EEPROM:
spur_val = EEP_MAP9287_SPURCHAN; spur_val = EEP_MAP9287_SPURCHAN;
......
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...@@ -103,8 +103,8 @@ static int ath_register_led(struct ath_softc *sc, struct ath_led *led, ...@@ -103,8 +103,8 @@ static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev); ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
if (ret) if (ret)
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, ath_err(ath9k_hw_common(sc->sc_ah),
"Failed to register led:%s", led->name); "Failed to register led:%s", led->name);
else else
led->registered = 1; led->registered = 1;
return ret; return ret;
...@@ -236,13 +236,13 @@ static void ath_detect_bt_priority(struct ath_softc *sc) ...@@ -236,13 +236,13 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN); sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN);
/* Detect if colocated bt started scanning */ /* Detect if colocated bt started scanning */
if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX, ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
"BT scan detected"); "BT scan detected\n");
sc->sc_flags |= (SC_OP_BT_SCAN | sc->sc_flags |= (SC_OP_BT_SCAN |
SC_OP_BT_PRIORITY_DETECTED); SC_OP_BT_PRIORITY_DETECTED);
} else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX, ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
"BT priority traffic detected"); "BT priority traffic detected\n");
sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED; sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
} }
...@@ -331,8 +331,8 @@ static void ath_btcoex_no_stomp_timer(void *arg) ...@@ -331,8 +331,8 @@ static void ath_btcoex_no_stomp_timer(void *arg)
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN; bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN;
ath_print(common, ATH_DBG_BTCOEX, ath_dbg(common, ATH_DBG_BTCOEX,
"no stomp timer running\n"); "no stomp timer running\n");
spin_lock_bh(&btcoex->btcoex_lock); spin_lock_bh(&btcoex->btcoex_lock);
...@@ -378,8 +378,8 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc) ...@@ -378,8 +378,8 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc)
struct ath_btcoex *btcoex = &sc->btcoex; struct ath_btcoex *btcoex = &sc->btcoex;
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX, ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
"Starting btcoex timers"); "Starting btcoex timers\n");
/* make sure duty cycle timer is also stopped when resuming */ /* make sure duty cycle timer is also stopped when resuming */
if (btcoex->hw_timer_enabled) if (btcoex->hw_timer_enabled)
......
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