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Commit 6421d89f authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-arm64-dt-for-v4.14' of... 

Merge tag 'renesas-arm64-dt-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Pull "Renesas ARM64 Based SoC DT Updates for v4.14" from Simon Horman:

* Add usb2.0 for R-Car H3 (r8a7795) ES2.0 SoC

* Add R-Car D3 (r8a77995) SoC and Draak board support

  Adds minimal support for the R-Car D3 SoC and the Draak development
  board, allowing to boot from a ramdisk using a serial console.

* Add Add VC6 clock generator to R-Car H3 (r8a7795)/Salvator-XS board

  The VC6 is an I2C-controlled programmable clock generator, used on the
  board to provide a display dot clock. Add it to DT.

* Add missing second pair of DMA names to MSIOF nodes to
  R-Car M3-W (r8a7796) SoC

  MSIOF0 and MSIOF1 are tied to two DMA controllers through two pairs of
  DMA specifiers.  However, the second pair of corresponding DMA names was
  missing.

* Add support for the DU to R-Car H3 (r8a7795) SoC

  Add a compatible string and VSP links to the DU node. The H3 ES1.x and H3
  ES2.0 are compatible save for the links to the VSPs that are described
  explicitly in DT, so there's no need for a new ES2-specific compatible
  string.

* Enable HDMI on R-Car H3 (r8a7795) and M3-W (r8a7796) ULCB boards

* Enable DU on R-Car M3-W (r8a7796) Salvator-X board

* Enable I2C for DVFS on R-Car H3 (r8a7795) and M3-W (r8a7796) ULCB boards

* Add Add DRIF support to R-Car H3 (r8a7795) and M3-W (r8a7796) SoCs

  Ramesh Shanmugasundaram says, "R-Car Gen3 DRIF is a SPI like receive only
  slave device."

* Move CPG_AUDIO_CLK_I from board to soc files

  Geert Uytterhoeven says, "The definition of CPG_AUDIO_CLK_I is
  SoC-specific, not board-specific."

* Add IMR-LX4 support to R-Car H3 (r8a7795) and M3-W (r8a7796) SoCs

  Sergei Shtylyov says, "The image renderer light extended 4 (IMR-LX4) or
  the distortion correction engine is a drawing processor with a simple
  instruction system capable of referencing data on an external memory as
  2D texture data and performing texture mapping and drawing with respect
  to any shape that is split into triangular objects."

* tag 'renesas-arm64-dt-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits)
  arm64: dts: renesas: r8a7795: add hsusb ch3 device node
  arm64: dts: renesas: r8a7795: add usb-dmac ch2 and ch3 device nodes
  arm64: dts: renesas: r8a7795: add usb2.0 host ch3 device nodes
  arm64: dts: renesas: r8a7795: add usb2_phy ch3 device node
  arm64: dts: renesas: r8a7795: Add usb companion property in EHCI
  arm64: dts: renesas: Add Renesas Draak board support
  arm64: dts: renesas: Add Renesas R8A77995 SoC support
  arm64: renesas: Add Renesas R8A77995 Kconfig support
  arm64: dts: r8a7795: salvator-xs: Connect DU dot clocks 0 and 3
  arm64: dts: salvator-xs: Add VC6 clock generator
  arm64: dts: r8a7796: Add missing second pair of DMA names to MSIOF nodes
  arm64: dts: r8a7795: Add all MSIOF nodes
  arm64: dts: r8a7795: Add support for the DU
  arm64: dts: ulcb: Enable HDMI output
  arm64: dts: ulcb: Add HDMI output connector
  arm64: dts: r8a7796: m3ulcb: Add DU external dot clocks
  arm64: dts: r8a7795: h3ulcb: Add DU external dot clocks
  arm64: dts: ulcb: Add DU external dot clock sources
  arm64: dts: r8a7796: salvator-x: Enable HDMI output
  arm64: dts: r8a7796: salvator-x: Add DU external dot clocks
  ...
parents 34a39ff1 4725f2b8
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arch/arm64/Kconfig.platforms
View file @ 6421d89f
......@@ -184,6 +184,12 @@ config ARCH_R8A7796
help
This enables support for the Renesas R-Car M3-W SoC.
config ARCH_R8A77995
bool "Renesas R-Car D3 SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car D3 SoC.
config ARCH_STRATIX10
bool "Altera's Stratix 10 SoCFPGA Family"
help
......
arch/arm64/boot/dts/renesas/Makefile
View file @ 6421d89f
......@@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
always := $(dtb-y)
clean-files := *.dtb
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
View file @ 6421d89f
......@@ -9,8 +9,6 @@
* kind, whether express or implied.
*/
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
/dts-v1/;
#include "r8a7795-es1.dtsi"
#include "ulcb.dtsi"
......
arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
View file @ 6421d89f
......@@ -8,8 +8,6 @@
* kind, whether express or implied.
*/
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
/dts-v1/;
#include "r8a7795-es1.dtsi"
#include "salvator-x.dtsi"
......
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
View file @ 6421d89f
......@@ -21,6 +21,14 @@ xhci1: usb@ee0400000 {
status = "disabled";
};
/delete-node/ usb-phy@ee0e0200;
/delete-node/ usb@ee0e0100;
/delete-node/ usb@ee0e0000;
/delete-node/ usb@e659c000;
/delete-node/ dma-controller@e6460000;
/delete-node/ dma-controller@e6470000;
fcpf2: fcp@fe952000 {
compatible = "renesas,fcpf";
reg = <0 0xfe952000 0 0x200>;
......@@ -79,6 +87,5 @@ fdp1@fe948000 {
};
&du {
compatible = "renesas,du-r8a7795";
vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
};
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
View file @ 6421d89f
......@@ -9,8 +9,6 @@
* kind, whether express or implied.
*/
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
/dts-v1/;
#include "r8a7795.dtsi"
#include "ulcb.dtsi"
......@@ -40,3 +38,17 @@ memory@700000000 {
reg = <0x7 0x00000000 0x0 0x40000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 4>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
View file @ 6421d89f
......@@ -8,8 +8,6 @@
* kind, whether express or implied.
*/
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
/dts-v1/;
#include "r8a7795.dtsi"
#include "salvator-x.dtsi"
......
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
View file @ 6421d89f
......@@ -8,8 +8,6 @@
* kind, whether express or implied.
*/
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
/dts-v1/;
#include "r8a7795.dtsi"
#include "salvator-xs.dtsi"
......@@ -46,10 +44,12 @@ &du {
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock6 1>,
<&x21_clk>,
<&x22_clk>;
<&x22_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
"dclkin.1", "dclkin.2";
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
&ehci2 {
......
arch/arm64/boot/dts/renesas/r8a7795.dtsi
View file @ 6421d89f
This diff is collapsed.
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
View file @ 6421d89f
......@@ -9,8 +9,6 @@
* kind, whether express or implied.
*/
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
/dts-v1/;
#include "r8a7796.dtsi"
#include "ulcb.dtsi"
......@@ -30,3 +28,15 @@ memory@600000000 {
reg = <0x6 0x00000000 0x0 0x40000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "lvds.0",
"dclkin.0", "dclkin.1", "dclkin.2";
};
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
View file @ 6421d89f
......@@ -8,8 +8,6 @@
* kind, whether express or implied.
*/
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
/dts-v1/;
#include "r8a7796.dtsi"
#include "salvator-x.dtsi"
......@@ -29,3 +27,32 @@ memory@600000000 {
reg = <0x6 0x00000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&x21_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "lvds.0",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
arch/arm64/boot/dts/renesas/r8a7796.dtsi
View file @ 6421d89f
......@@ -12,6 +12,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7796-sysc.h>
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
/ {
compatible = "renesas,r8a7796";
#address-cells = <2>;
......@@ -639,6 +641,126 @@ channel1 {
};
};
drif00: rif@e6f40000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f40000 0 0x64>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>;
clock-names = "fck";
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 515>;
renesas,bonding = <&drif01>;
status = "disabled";
};
drif01: rif@e6f50000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f50000 0 0x64>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>;
clock-names = "fck";
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 514>;
renesas,bonding = <&drif00>;
status = "disabled";
};
drif10: rif@e6f60000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f60000 0 0x64>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 513>;
clock-names = "fck";
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 513>;
renesas,bonding = <&drif11>;
status = "disabled";
};
drif11: rif@e6f70000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f70000 0 0x64>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 512>;
clock-names = "fck";
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 512>;
renesas,bonding = <&drif10>;
status = "disabled";
};
drif20: rif@e6f80000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f80000 0 0x64>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 511>;
clock-names = "fck";
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 511>;
renesas,bonding = <&drif21>;
status = "disabled";
};
drif21: rif@e6f90000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f90000 0 0x64>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 510>;
clock-names = "fck";
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 510>;
renesas,bonding = <&drif20>;
status = "disabled";
};
drif30: rif@e6fa0000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fa0000 0 0x64>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 509>;
clock-names = "fck";
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 509>;
renesas,bonding = <&drif31>;
status = "disabled";
};
drif31: rif@e6fb0000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fb0000 0 0x64>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 508>;
clock-names = "fck";
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 508>;
renesas,bonding = <&drif30>;
status = "disabled";
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7796",
"renesas,etheravb-rcar-gen3";
......@@ -877,7 +999,7 @@ msiof0: spi@e6e90000 {
clocks = <&cpg CPG_MOD 211>;
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx";
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 211>;
#address-cells = <1>;
......@@ -893,7 +1015,7 @@ msiof1: spi@e6ea0000 {
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx";
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
......@@ -1440,8 +1562,150 @@ pciec1: pcie@ee800000 {
/* placeholder */
};
fcpf0: fcp@fe950000 {
compatible = "renesas,fcpf";
reg = <0 0xfe950000 0 0x200>;
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 615>;
};
vspb: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 626>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 626>;
renesas,fcp = <&fcpvb0>;
};
fcpvb0: fcp@fe96f000 {
compatible = "renesas,fcpv";
reg = <0 0xfe96f000 0 0x200>;
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 607>;
};
vspi0: vsp@fe9a0000 {
compatible = "renesas,vsp2";
reg = <0 0xfe9a0000 0 0x8000>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 631>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 631>;
renesas,fcp = <&fcpvi0>;
};
fcpvi0: fcp@fe9af000 {
compatible = "renesas,fcpv";
reg = <0 0xfe9af000 0 0x200>;
clocks = <&cpg CPG_MOD 611>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 611>;
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x4000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 623>;
renesas,fcp = <&fcpvd0>;
};
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 603>;
};
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
reg = <0 0xfea28000 0 0x4000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 622>;
renesas,fcp = <&fcpvd1>;
};
fcpvd1: fcp@fea2f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 602>;
};
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
reg = <0 0xfea30000 0 0x4000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 621>;
renesas,fcp = <&fcpvd2>;
};
fcpvd2: fcp@fea37000 {
compatible = "renesas,fcpv";
reg = <0 0xfea37000 0 0x200>;
clocks = <&cpg CPG_MOD 601>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 601>;
};
hdmi0: hdmi@fead0000 {
compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
reg = <0 0xfead0000 0 0x10000>;
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
clock-names = "iahb", "isfr";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 729>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dw_hdmi0_in: endpoint {
remote-endpoint = <&du_out_hdmi0>;
};
};
port@1 {
reg = <1>;
};
};
};
du: display@feb00000 {
/* placeholder */
compatible = "renesas,du-r8a7796";
reg = <0 0xfeb00000 0 0x70000>,
<0 0xfeb90000 0 0x14>;
reg-names = "du", "lvds.0";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 727>;
clock-names = "du.0", "du.1", "du.2", "lvds.0";
status = "disabled";
vsps = <&vspd0 &vspd1 &vspd2>;
ports {
#address-cells = <1>;
......@@ -1452,7 +1716,38 @@ port@0 {
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
du_out_hdmi0: endpoint {
remote-endpoint = <&dw_hdmi0_in>;
};
};
port@2 {
reg = <2>;
du_out_lvds0: endpoint {
};
};
};
};
imr-lx4@fe860000 {
compatible = "renesas,r8a7796-imr-lx4",
"renesas,imr-lx4";
reg = <0 0xfe860000 0 0x2000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 823>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 823>;
};
imr-lx4@fe870000 {
compatible = "renesas,r8a7796-imr-lx4",
"renesas,imr-lx4";
reg = <0 0xfe870000 0 0x2000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 822>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 822>;
};
};
};
arch/arm64/boot/dts/renesas/r8a77995-draak.dts 0 → 100644
View file @ 6421d89f
/*
* Device Tree Source for the Draak board
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a77995.dtsi"
/ {
model = "Renesas Draak board based on r8a77995";
compatible = "renesas,draak", "renesas,r8a77995";
aliases {
serial0 = &scif2;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x18000000>;
};
};
&extal_clk {
clock-frequency = <48000000>;
};
&scif2 {
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
arch/arm64/boot/dts/renesas/r8a77995.dtsi 0 → 100644
View file @ 6421d89f
/*
* Device Tree Source for the r8a77995 SoC
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "renesas,r8a77995";
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
a53_0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc 5>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA53: cache-controller-1 {
compatible = "cache";
power-domains = <&sysc 21>;
cache-unified;
cache-level = <2>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc 32>;
resets = <&cpg 408>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77995-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc 32>;
resets = <&cpg 402>;
status = "disabled";
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77995-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77995-rst";
reg = <0 0xe6160000 0 0x0200>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77995-sysc";
reg = <0 0xe6180000 0 0x0400>;
#power-domain-cells = <1>;
};
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77995",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE 16>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc 32>;
resets = <&cpg 310>;
status = "disabled";
};
};
};
arch/arm64/boot/dts/renesas/salvator-xs.dtsi
View file @ 6421d89f
......@@ -18,3 +18,13 @@ / {
&extal_clk {
clock-frequency = <16640000>;
};
&i2c4 {
versaclock6: clock-generator@6a {
compatible = "idt,5p49v6901";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x23_clk>;
clock-names = "xin";
};
};
arch/arm64/boot/dts/renesas/ulcb.dtsi
View file @ 6421d89f
......@@ -34,6 +34,16 @@ audio_clkout: audio-clkout {
clock-frequency = <11289600>;
};
hdmi0-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con: endpoint {
};
};
};
keyboard {
compatible = "gpio-keys";
......@@ -120,6 +130,12 @@ x12_clk: x12 {
#clock-cells = <0>;
clock-frequency = <24576000>;
};
x23_clk: x23-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
&audio_clk_a {
......@@ -153,6 +169,23 @@ &extalr_clk {
clock-frequency = <32768>;
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
......@@ -189,6 +222,24 @@ cs2000: clk-multiplier@4f {
};
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
versaclock5: clock-generator@6a {
compatible = "idt,5p49v5925";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x23_clk>;
clock-names = "xin";
};
};
&i2c_dvfs {
status = "okay";
};
&ohci1 {
status = "okay";
};
......
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