Commit 65348659 authored by Fabrice Gasnier's avatar Fabrice Gasnier Committed by Greg Kroah-Hartman

pwm: stm32-lp: Add check in case requested period cannot be achieved

[ Upstream commit c91e3234 ]

LPTimer can use a 32KHz clock for counting. It depends on clock tree
configuration. In such a case, PWM output frequency range is limited.
Although unlikely, nothing prevents user from requesting a PWM frequency
above counting clock (32KHz for instance):
- This causes (prd - 1) = 0xffff to be written in ARR register later in
the apply() routine.
This results in badly configured PWM period (and also duty_cycle).
Add a check to report an error is such a case.
Signed-off-by: default avatarFabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 19b1c70e
...@@ -58,6 +58,12 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, ...@@ -58,6 +58,12 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
/* Calculate the period and prescaler value */ /* Calculate the period and prescaler value */
div = (unsigned long long)clk_get_rate(priv->clk) * state->period; div = (unsigned long long)clk_get_rate(priv->clk) * state->period;
do_div(div, NSEC_PER_SEC); do_div(div, NSEC_PER_SEC);
if (!div) {
/* Clock is too slow to achieve requested period. */
dev_dbg(priv->chip.dev, "Can't reach %u ns\n", state->period);
return -EINVAL;
}
prd = div; prd = div;
while (div > STM32_LPTIM_MAX_ARR) { while (div > STM32_LPTIM_MAX_ARR) {
presc++; presc++;
......
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