drm: panel: simple: Set enable delay for BOE NV110WTM-N61

Panel power sequence says timing T8 (time from link idle to turn on
the backlight) should be at least 50 ms.  This is what the .enable
delay in simple-panel is for, so set it.  NOTE: this overlaps with the
80 ms .prepare_to_enable delay on purpose.  The data sheet says that
at least 80 ms needs to pass between HPD going high and turning on the
backlight and that at least 50 ms needs to pass between the link idle
and the backlight going on.  Thus it works like this on the system in
front of me:
* In bridge chip pre_enable call drm_panel_prepare()
* drm_panel_prepare() -> panel_simple_prepare()
* Wait for HPD GPIO to go high.
* Start counting for 80 ms (store in prepared_time)
* In bridge chip enable, train link then call drm_panel_enable()
* drm_panel_enable() -> panel_simple_enable()
* panel_simple_enable() does hardcoded 50 ms delay then enforces 80 ms
  from HPD going high (in case the bridge took less than 30 ms to
  enable / link train).
* drm_panel_enable() -> backlight_enable().
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20210222081716.1.I1a45aece5d2ac6a2e73bbec50da2086e43e0862b@changeid

drivers/gpu/drm/panel/panel-simple.c

@@ -1484,6 +1484,7 @@ static const struct panel_desc boe_nv110wtm_n61 = {
 	.delay = {
 		.hpd_absent_delay = 200,
 		.prepare_to_enable = 80,
+		.enable = 50,
 		.unprepare = 500,
 	},
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,