Commit 6810ed32 authored by Felix Fietkau's avatar Felix Fietkau Committed by Paul Burton

MIPS: ath79: export switch MDIO reference clock

On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
clock. If that feature is not used, it defaults to the main reference
clock, like on all other SoC.
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
Signed-off-by: default avatarJohn Crispin <john@phrozen.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
parent e7eea04d
...@@ -42,6 +42,7 @@ static const char * const clk_names[ATH79_CLK_END] = { ...@@ -42,6 +42,7 @@ static const char * const clk_names[ATH79_CLK_END] = {
[ATH79_CLK_DDR] = "ddr", [ATH79_CLK_DDR] = "ddr",
[ATH79_CLK_AHB] = "ahb", [ATH79_CLK_AHB] = "ahb",
[ATH79_CLK_REF] = "ref", [ATH79_CLK_REF] = "ref",
[ATH79_CLK_MDIO] = "mdio",
}; };
static const char * __init ath79_clk_name(int type) static const char * __init ath79_clk_name(int type)
...@@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(void __iomem *pll_base) ...@@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(void __iomem *pll_base)
ath79_set_clk(ATH79_CLK_DDR, ddr_rate); ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate); ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
iounmap(dpll_base); iounmap(dpll_base);
} }
...@@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt(struct device_node *np) ...@@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
else if (of_device_is_compatible(np, "qca,qca9560-pll")) else if (of_device_is_compatible(np, "qca,qca9560-pll"))
qca956x_clocks_init(pll_base); qca956x_clocks_init(pll_base);
if (!clks[ATH79_CLK_MDIO])
clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
pr_err("%pOF: could not register clk provider\n", np); pr_err("%pOF: could not register clk provider\n", np);
goto err_iounmap; goto err_iounmap;
......
...@@ -14,7 +14,8 @@ ...@@ -14,7 +14,8 @@
#define ATH79_CLK_DDR 1 #define ATH79_CLK_DDR 1
#define ATH79_CLK_AHB 2 #define ATH79_CLK_AHB 2
#define ATH79_CLK_REF 3 #define ATH79_CLK_REF 3
#define ATH79_CLK_MDIO 4
#define ATH79_CLK_END 4 #define ATH79_CLK_END 5
#endif /* __DT_BINDINGS_ATH79_CLK_H */ #endif /* __DT_BINDINGS_ATH79_CLK_H */
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