Revert "x86/cpu/AMD: Add speculative control support for AMD"

CVE-2017-5753 (revert embargoed)
CVE-2017-5715 (revert embargoed)

This reverts commit 0c42069d.
Signed-off-by: Andy Whitcroft <apw@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

arch/x86/include/asm/cpufeatures.h

@@ -243,7 +243,6 @@
 
 /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
 #define X86_FEATURE_CQM_LLC	(11*32+ 1) /* LLC QoS if 1 */
-#define X86_FEATURE_IBPB	(13*32+12) /* Indirect Branch Prediction Barrier */
 
 /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
 #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */

arch/x86/include/asm/msr-index.h

@@ -333,7 +333,6 @@
 #define MSR_F15H_NB_PERF_CTL		0xc0010240
 #define MSR_F15H_NB_PERF_CTR		0xc0010241
 #define MSR_F15H_IC_CFG			0xc0011021
-#define MSR_F15H_IC_CFG_DIS_IND		BIT_ULL(14)
 
 /* Fam 10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058

arch/x86/kernel/cpu/amd.c

@@ -769,45 +769,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 
 	/* AMD CPUs don't reset SS attributes on SYSRET */
 	set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
-
-	/* AMD speculative control support */
-	if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
-		pr_info_once("FEATURE SPEC_CTRL Present\n");
-		set_ibrs_supported();
-		set_ibpb_supported();
-		if (ibrs_inuse)
-			sysctl_ibrs_enabled = 1;
-		if (ibpb_inuse)
-			sysctl_ibpb_enabled = 1;
-	} else if (cpu_has(c, X86_FEATURE_IBPB)) {
-		pr_info_once("FEATURE SPEC_CTRL Not Present\n");
-		pr_info_once("FEATURE IBPB Present\n");
-		set_ibpb_supported();
-		if (ibpb_inuse)
-			sysctl_ibpb_enabled = 1;
-	} else {
-		pr_info_once("FEATURE SPEC_CTRL Not Present\n");
-		pr_info_once("FEATURE IBPB Not Present\n");
-		/*
-		 * On AMD processors that do not support the speculative
-		 * control features, IBPB type support can be achieved by
-		 * disabling indirect branch predictor support.
-		 */
-		if (!ibpb_disabled) {
-			u64 val;
-
-			switch (c->x86) {
-			case 0x10:
-			case 0x12:
-			case 0x16:
-				pr_info_once("Disabling indirect branch predictor support\n");
-				rdmsrl(MSR_F15H_IC_CFG, val);
-				val |= MSR_F15H_IC_CFG_DIS_IND;
-				wrmsrl(MSR_F15H_IC_CFG, val);
-				break;
-			}
-		}
-	}
 }
 
 #ifdef CONFIG_X86_32