ARM: dts: rockchip: add both clocks to uart nodes

Use the newly ammended dw_8250 clock binding to define both the baudclk as
well as the pclk supplying the ip.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

arch/arm/boot/dts/rk3xxx.dtsi

@@ -75,7 +75,8 @@ uart0: serial@10124000 {
 		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 		reg-shift = <2>;
 		reg-io-width = <1>;
-		clocks = <&cru SCLK_UART0>;
+		clock-names = "baudclk", "apb_pclk";
+		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 		status = "disabled";
 	};
 
@@ -85,7 +86,8 @@ uart1: serial@10126000 {
 		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 		reg-shift = <2>;
 		reg-io-width = <1>;
-		clocks = <&cru SCLK_UART1>;
+		clock-names = "baudclk", "apb_pclk";
+		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 		status = "disabled";
 	};
 
@@ -207,7 +209,8 @@ uart2: serial@20064000 {
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		reg-shift = <2>;
 		reg-io-width = <1>;
-		clocks = <&cru SCLK_UART2>;
+		clock-names = "baudclk", "apb_pclk";
+		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 		status = "disabled";
 	};
 
@@ -217,7 +220,8 @@ uart3: serial@20068000 {
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		reg-shift = <2>;
 		reg-io-width = <1>;
-		clocks = <&cru SCLK_UART3>;
+		clock-names = "baudclk", "apb_pclk";
+		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 		status = "disabled";
 	};
 };