ARM: dts: uniphier: add Denali NAND controller node

Add NAND controller node to LD4, Pro4, sLD8, Pro5, and PXs2.
Set up pinctrl to enable 2 chip select lines except Pro4.  The CS1
for Pro4 is multiplexed with other peripherals such as UART2, so
I did not enable it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arch/arm/boot/dts/uniphier-ld4-ref.dts

@@ -64,3 +64,7 @@ &usb0 {
 &usb1 {
 	status = "okay";
 };
+
+&nand {
+	status = "okay";
+};

arch/arm/boot/dts/uniphier-ld4.dtsi

@@ -285,6 +285,17 @@ sys_rst: reset {
 				#reset-cells = <1>;
 			};
 		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,uniphier-denali-nand-v5a";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand2cs>;
+			clocks = <&sys_clk 2>;
+		};
 	};
 };
 

arch/arm/boot/dts/uniphier-ld6b-ref.dts

@@ -58,3 +58,7 @@ &serial2 {
 &i2c0 {
 	status = "okay";
 };
+
+&nand {
+	status = "okay";
+};

arch/arm/boot/dts/uniphier-pro4-ref.dts

@@ -66,3 +66,7 @@ &usb2 {
 &usb3 {
 	status = "okay";
 };
+
+&nand {
+	status = "okay";
+};

arch/arm/boot/dts/uniphier-pro4.dtsi

@@ -305,6 +305,17 @@ sys_rst: reset {
 				#reset-cells = <1>;
 			};
 		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,uniphier-denali-nand-v5a";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+		};
 	};
 };
 

arch/arm/boot/dts/uniphier-pro5.dtsi

@@ -368,6 +368,17 @@ sys_rst: reset {
 				#reset-cells = <1>;
 			};
 		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,uniphier-denali-nand-v5b";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand2cs>;
+			clocks = <&sys_clk 2>;
+		};
 	};
 };
 

arch/arm/boot/dts/uniphier-pxs2.dtsi

@@ -352,6 +352,17 @@ sys_rst: reset {
 				#reset-cells = <1>;
 			};
 		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,uniphier-denali-nand-v5b";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand2cs>;
+			clocks = <&sys_clk 2>;
+		};
 	};
 };
 

arch/arm/boot/dts/uniphier-sld8-ref.dts

@@ -68,3 +68,7 @@ &usb1 {
 &usb2 {
 	status = "okay";
 };
+
+&nand {
+	status = "okay";
+};

arch/arm/boot/dts/uniphier-sld8.dtsi

@@ -285,6 +285,17 @@ sys_rst: reset {
 				#reset-cells = <1>;
 			};
 		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,uniphier-denali-nand-v5a";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand2cs>;
+			clocks = <&sys_clk 2>;
+		};
 	};
 };