drm/bridge: tc358768: fix PLL parameters computation
According to Toshiba documentation the PLL input clock after the divider should be not less than 4MHz, fix the PLL parameters computation accordingly. Fixes: ff1ca639 ("drm/bridge: Add tc358768 driver") Signed-off-by:Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by:
Robert Foss <rfoss@kernel.org> Signed-off-by:
Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230427142934.55435-3-francesco@dolcini.it
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