Commit 6a4ccd9a authored by Beniamino Galvani's avatar Beniamino Galvani Committed by Carlo Caione

ARM: meson: enable L2 cache

This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: default avatarBeniamino Galvani <b.galvani@gmail.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarCarlo Caione <carlo@caione.org>
parent a25a6772
...@@ -2,6 +2,7 @@ menuconfig ARCH_MESON ...@@ -2,6 +2,7 @@ menuconfig ARCH_MESON
bool "Amlogic Meson SoCs" if ARCH_MULTI_V7 bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
select GENERIC_IRQ_CHIP select GENERIC_IRQ_CHIP
select ARM_GIC select ARM_GIC
select CACHE_L2X0
if ARCH_MESON if ARCH_MESON
......
...@@ -24,4 +24,6 @@ static const char * const meson_common_board_compat[] = { ...@@ -24,4 +24,6 @@ static const char * const meson_common_board_compat[] = {
DT_MACHINE_START(MESON, "Amlogic Meson platform") DT_MACHINE_START(MESON, "Amlogic Meson platform")
.dt_compat = meson_common_board_compat, .dt_compat = meson_common_board_compat,
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
MACHINE_END MACHINE_END
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