Commit 6a79162f authored by bilbao@vt.edu's avatar bilbao@vt.edu Committed by Jonathan Corbet

docs: Fix typo in Documentation/x86/x86_64/5level-paging.rst

fix two typos in the documentation
(Documentation/x86/x86_64/5level-paging.rst), changing 'paing' for 'paging'
and using the right verbal form for plural on 'some vendors offer'.
Signed-off-by: default avatarCarlos Bilbao <bilbao@vt.edu>
Link: https://lore.kernel.org/r/2599991.mvXUDI8C0e@iron-maidenSigned-off-by: default avatarJonathan Corbet <corbet@lwn.net>
parent 80342d48
...@@ -6,9 +6,9 @@ ...@@ -6,9 +6,9 @@
Overview Overview
======== ========
Original x86-64 was limited by 4-level paing to 256 TiB of virtual address Original x86-64 was limited by 4-level paging to 256 TiB of virtual address
space and 64 TiB of physical address space. We are already bumping into space and 64 TiB of physical address space. We are already bumping into
this limit: some vendors offers servers with 64 TiB of memory today. this limit: some vendors offer servers with 64 TiB of memory today.
To overcome the limitation upcoming hardware will introduce support for To overcome the limitation upcoming hardware will introduce support for
5-level paging. It is a straight-forward extension of the current page 5-level paging. It is a straight-forward extension of the current page
......
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