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Commit 6af50f5a authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-dts-for-v6.8-tag2' of... 

Merge tag 'renesas-dts-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.8 (take two)

  - Add IA55 interrupt controller and Ethernet support for the RZ/G3S
    SoC and the RZ/G3S SMARC SoM,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: white-hawk-cpu: Fix missing serial console pin control
  arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces
  arm64: dts: renesas: rzg3s-smarc-som: Use switches' names to select on-board functionalities
  arm64: dts: renesas: r9a08g045: Add Ethernet nodes
  arm64: dts: renesas: r9a08g045: Add IA55 interrupt controller node

Link: https://lore.kernel.org/r/cover.1702642342.git.geert+renesas@glider.beSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 084d415d fc674956
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Showing with 269 additions and 13 deletions
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
View file @ 6af50f5a
......@@ -187,6 +187,9 @@ &extalr_clk {
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
status = "okay";
};
......
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
View file @ 6af50f5a
......@@ -96,6 +96,7 @@ pinctrl: pinctrl@11030000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&irqc>;
gpio-ranges = <&pinctrl 0 0 152>;
clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
power-domains = <&cpg>;
......@@ -104,6 +105,73 @@ pinctrl: pinctrl@11030000 {
<&cpg R9A08G045_GPIO_SPARE_RESETN>;
};
irqc: interrupt-controller@11050000 {
compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x11050000 0 0x10000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"tint0", "tint1", "tint2", "tint3",
"tint4", "tint5", "tint6", "tint7",
"tint8", "tint9", "tint10", "tint11",
"tint12", "tint13", "tint14", "tint15",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err";
clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
<&cpg CPG_MOD R9A08G045_IA55_PCLK>;
clock-names = "clk", "pclk";
power-domains = <&cpg>;
resets = <&cpg R9A08G045_IA55_RESETN>;
};
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
......@@ -149,6 +217,44 @@ sdhi2: mmc@11c20000 {
status = "disabled";
};
eth0: ethernet@11c30000 {
compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
reg = <0 0x11c30000 0 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
<&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
<&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
eth1: ethernet@11c40000 {
compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
reg = <0 0x11c40000 0 0x10000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
<&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
<&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@12400000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
......
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
View file @ 6af50f5a
......@@ -9,24 +9,35 @@
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/*
* Signals of SW_CONFIG switches:
* @SW_SD0_DEV_SEL:
* 0 - SD0 is connected to eMMC
* 1 - SD0 is connected to uSD0 card
* @SW_SD2_EN:
* 0 - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
* 1 - SD2 is connected to SoC
* On-board switches' states:
* @SW_OFF: switch's state is OFF
* @SW_ON: switch's state is ON
*/
#define SW_SD0_DEV_SEL 1
#define SW_SD2_EN 1
#define SW_OFF 0
#define SW_ON 1
/*
* SW_CONFIG[x] switches' states:
* @SW_CONFIG2:
* SW_OFF - SD0 is connected to eMMC
* SW_ON - SD0 is connected to uSD0 card
* @SW_CONFIG3:
* SW_OFF - SD2 is connected to SoC
* SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
*/
#define SW_CONFIG2 SW_ON
#define SW_CONFIG3 SW_ON
/ {
compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
aliases {
mmc0 = &sdhi0;
#if SW_SD2_EN
#if SW_CONFIG3 == SW_OFF
mmc2 = &sdhi2;
#else
eth0 = &eth0;
eth1 = &eth1;
#endif
};
......@@ -50,7 +61,7 @@ vcc_sdhi0: regulator0 {
enable-active-high;
};
#if SW_SD0_DEV_SEL
#if SW_CONFIG2 == SW_ON
vccq_sdhi0: regulator1 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
......@@ -81,11 +92,65 @@ vcc_sdhi2: regulator2 {
};
};
#if SW_CONFIG3 == SW_ON
&eth0 {
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@7 {
reg = <7>;
interrupt-parent = <&pinctrl>;
interrupts = <RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&eth1 {
pinctrl-0 = <&eth1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
phy1: ethernet-phy@7 {
reg = <7>;
interrupt-parent = <&pinctrl>;
interrupts = <RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
#endif
&extal_clk {
clock-frequency = <24000000>;
};
#if SW_SD0_DEV_SEL
#if SW_CONFIG2 == SW_ON
/* SD0 slot */
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
......@@ -116,7 +181,7 @@ &sdhi0 {
};
#endif
#if SW_SD2_EN
#if SW_CONFIG3 == SW_OFF
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default";
......@@ -128,6 +193,88 @@ &sdhi2 {
#endif
&pinctrl {
eth0-phy-irq-hog {
gpio-hog;
gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
input;
line-name = "eth0-phy-irq";
};
eth0_pins: eth0 {
txc {
pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */
power-source = <1800>;
output-enable;
input-enable;
drive-strength-microamp = <5200>;
};
tx_ctl {
pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */
power-source = <1800>;
output-enable;
drive-strength-microamp = <5200>;
};
mux {
pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(4, 5, 1)>; /* ET0_LINKSTA */
power-source = <1800>;
};
};
eth1-phy-irq-hog {
gpio-hog;
gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
input;
line-name = "eth1-phy-irq";
};
eth1_pins: eth1 {
txc {
pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */
power-source = <1800>;
output-enable;
input-enable;
drive-strength-microamp = <5200>;
};
tx_ctl {
pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>; /* ET1_TX_CTL */
power-source = <1800>;
output-enable;
drive-strength-microamp = <5200>;
};
mux {
pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
<RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(10, 4, 1)>; /* ET1_LINKSTA */
power-source = <1800>;
};
};
sdhi0_pins: sd0 {
data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
......
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