Commit 6b726a0a authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/pm/smu_v11.0: update IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1fcc208c
...@@ -116,12 +116,12 @@ int smu_v11_0_init_microcode(struct smu_context *smu) ...@@ -116,12 +116,12 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
case IP_VERSION(11, 0, 13): case IP_VERSION(11, 0, 13):
chip_name = "beige_goby"; chip_name = "beige_goby";
break; break;
case IP_VERSION(11, 0, 2):
chip_name = "arcturus";
break;
default: default:
if (adev->asic_type == CHIP_ARCTURUS) { dev_err(adev->dev, "Unsupported IP version 0x%x\n",
chip_name = "arcturus"; adev->ip_versions[MP1_HWIP]);
break;
}
dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
return -EINVAL; return -EINVAL;
} }
...@@ -267,12 +267,12 @@ int smu_v11_0_check_fw_version(struct smu_context *smu) ...@@ -267,12 +267,12 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
case IP_VERSION(11, 0, 8): case IP_VERSION(11, 0, 8):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
break; break;
case IP_VERSION(11, 0, 2):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
break;
default: default:
if (adev->asic_type == CHIP_ARCTURUS) { dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT; adev->ip_versions[MP1_HWIP]);
break;
}
dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
break; break;
} }
...@@ -1653,7 +1653,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) ...@@ -1653,7 +1653,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
default: default:
if (!ras || !adev->ras_enabled || if (!ras || !adev->ras_enabled ||
adev->gmc.xgmi.pending_reset) { adev->gmc.xgmi.pending_reset) {
if (adev->asic_type == CHIP_ARCTURUS) { if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT); data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
data |= 0x80000000; data |= 0x80000000;
WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data); WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
...@@ -1935,7 +1935,7 @@ int smu_v11_0_set_performance_level(struct smu_context *smu, ...@@ -1935,7 +1935,7 @@ int smu_v11_0_set_performance_level(struct smu_context *smu,
* Separate MCLK and SOCCLK soft min/max settings are not allowed * Separate MCLK and SOCCLK soft min/max settings are not allowed
* on Arcturus. * on Arcturus.
*/ */
if (adev->asic_type == CHIP_ARCTURUS) { if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
mclk_min = mclk_max = 0; mclk_min = mclk_max = 0;
socclk_min = socclk_max = 0; socclk_min = socclk_max = 0;
} }
......
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