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Commit 6c751372 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/bo: use NVIDIA's headers for move move() 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent e767835a
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Showing with 286 additions and 56 deletions
drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h 0 → 100644
View file @ 6c751372
This diff is collapsed.
drivers/gpu/drm/nouveau/nouveau_bo0039.c
View file @ 6c751372
......@@ -48,7 +48,9 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
{
struct nvif_push *push = chan->chan.push;
u32 src_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, old_reg);
u32 src_offset = old_reg->start << PAGE_SHIFT;
u32 dst_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, new_reg);
u32 dst_offset = new_reg->start << PAGE_SHIFT;
u32 page_count = new_reg->num_pages;
int ret;
......@@ -57,8 +59,8 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
if (ret)
return ret;
PUSH_NVSQ(push, NV039, 0x0184, nouveau_bo_mem_ctxdma(bo, chan, old_reg),
0x0188, nouveau_bo_mem_ctxdma(bo, chan, new_reg));
PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_BUFFER_IN, src_ctxdma,
SET_CONTEXT_DMA_BUFFER_OUT, dst_ctxdma);
page_count = new_reg->num_pages;
while (page_count) {
......@@ -68,15 +70,20 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
if (ret)
return ret;
PUSH_NVSQ(push, NV039, 0x030c, src_offset,
0x0310, dst_offset,
0x0314, PAGE_SIZE, /* src_pitch */
0x0318, PAGE_SIZE, /* dst_pitch */
0x031c, PAGE_SIZE, /* line_length */
0x0320, line_count,
0x0324, 0x00000101,
0x0328, 0x00000000);
PUSH_NVSQ(push, NV039, 0x0100, 0x00000000);
PUSH_MTHD(push, NV039, OFFSET_IN, src_offset,
OFFSET_OUT, dst_offset,
PITCH_IN, PAGE_SIZE,
PITCH_OUT, PAGE_SIZE,
LINE_LENGTH_IN, PAGE_SIZE,
LINE_COUNT, line_count,
FORMAT,
NVVAL(NV039, FORMAT, IN, 1) |
NVVAL(NV039, FORMAT, OUT, 1),
BUFFER_NOTIFY, NV039_BUFFER_NOTIFY_WRITE_ONLY);
PUSH_MTHD(push, NV039, NO_OPERATION, 0x00000000);
page_count -= line_count;
src_offset += (PAGE_SIZE * line_count);
......
drivers/gpu/drm/nouveau/nouveau_bo5039.c
View file @ 6c751372
......@@ -60,40 +60,70 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
height = amount / stride;
if (src_tiled) {
PUSH_NVSQ(push, NV5039, 0x0200, 0,
0x0204, 0,
0x0208, stride,
0x020c, height,
0x0210, 1,
0x0214, 0,
0x0218, 0);
PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, BLOCKLINEAR),
SET_SRC_BLOCK_SIZE,
NVDEF(NV5039, SET_SRC_BLOCK_SIZE, WIDTH, ONE_GOB) |
NVDEF(NV5039, SET_SRC_BLOCK_SIZE, HEIGHT, ONE_GOB) |
NVDEF(NV5039, SET_SRC_BLOCK_SIZE, DEPTH, ONE_GOB),
SET_SRC_WIDTH, stride,
SET_SRC_HEIGHT, height,
SET_SRC_DEPTH, 1,
SET_SRC_LAYER, 0,
SET_SRC_ORIGIN,
NVVAL(NV5039, SET_SRC_ORIGIN, X, 0) |
NVVAL(NV5039, SET_SRC_ORIGIN, Y, 0));
} else {
PUSH_NVSQ(push, NV5039, 0x0200, 1);
PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, PITCH));
}
if (dst_tiled) {
PUSH_NVSQ(push, NV5039, 0x021c, 0,
0x0220, 0,
0x0224, stride,
0x0228, height,
0x022c, 1,
0x0230, 0,
0x0234, 0);
PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, BLOCKLINEAR),
SET_DST_BLOCK_SIZE,
NVDEF(NV5039, SET_DST_BLOCK_SIZE, WIDTH, ONE_GOB) |
NVDEF(NV5039, SET_DST_BLOCK_SIZE, HEIGHT, ONE_GOB) |
NVDEF(NV5039, SET_DST_BLOCK_SIZE, DEPTH, ONE_GOB),
SET_DST_WIDTH, stride,
SET_DST_HEIGHT, height,
SET_DST_DEPTH, 1,
SET_DST_LAYER, 0,
SET_DST_ORIGIN,
NVVAL(NV5039, SET_DST_ORIGIN, X, 0) |
NVVAL(NV5039, SET_DST_ORIGIN, Y, 0));
} else {
PUSH_NVSQ(push, NV5039, 0x021c, 1);
PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, PITCH));
}
PUSH_NVSQ(push, NV5039, 0x0238, upper_32_bits(src_offset),
0x023c, upper_32_bits(dst_offset));
PUSH_NVSQ(push, NV5039, 0x030c, lower_32_bits(src_offset),
0x0310, lower_32_bits(dst_offset),
0x0314, stride,
0x0318, stride,
0x031c, stride,
0x0320, height,
0x0324, 0x00000101,
0x0328, 0x00000000);
PUSH_NVSQ(push, NV5039, 0x0100, 0x00000000);
PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER,
NVVAL(NV5039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)),
OFFSET_OUT_UPPER,
NVVAL(NV5039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset)));
PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset),
OFFSET_OUT, lower_32_bits(dst_offset),
PITCH_IN, stride,
PITCH_OUT, stride,
LINE_LENGTH_IN, stride,
LINE_COUNT, height,
FORMAT,
NVDEF(NV5039, FORMAT, IN, ONE) |
NVDEF(NV5039, FORMAT, OUT, ONE),
BUFFER_NOTIFY,
NVDEF(NV5039, BUFFER_NOTIFY, TYPE, WRITE_ONLY));
PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000);
length -= amount;
src_offset += amount;
......
drivers/gpu/drm/nouveau/nouveau_bo9039.c
View file @ 6c751372
......@@ -53,15 +53,27 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
if (ret)
return ret;
PUSH_NVSQ(push, NV9039, 0x0238, upper_32_bits(dst_offset),
0x023c, lower_32_bits(dst_offset));
PUSH_NVSQ(push, NV9039, 0x030c, upper_32_bits(src_offset),
0x0310, lower_32_bits(src_offset),
0x0314, PAGE_SIZE, /* src_pitch */
0x0318, PAGE_SIZE, /* dst_pitch */
0x031c, PAGE_SIZE, /* line_length */
0x0320, line_count);
PUSH_NVSQ(push, NV9039, 0x0300, 0x00100110);
PUSH_MTHD(push, NV9039, OFFSET_OUT_UPPER,
NVVAL(NV9039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset)),
OFFSET_OUT, lower_32_bits(dst_offset));
PUSH_MTHD(push, NV9039, OFFSET_IN_UPPER,
NVVAL(NV9039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)),
OFFSET_IN, lower_32_bits(src_offset),
PITCH_IN, PAGE_SIZE,
PITCH_OUT, PAGE_SIZE,
LINE_LENGTH_IN, PAGE_SIZE,
LINE_COUNT, line_count);
PUSH_MTHD(push, NV9039, LAUNCH_DMA,
NVDEF(NV9039, LAUNCH_DMA, SRC_INLINE, FALSE) |
NVDEF(NV9039, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |
NVDEF(NV9039, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |
NVDEF(NV9039, LAUNCH_DMA, COMPLETION_TYPE, FLUSH_DISABLE) |
NVDEF(NV9039, LAUNCH_DMA, INTERRUPT_TYPE, NONE) |
NVDEF(NV9039, LAUNCH_DMA, SEMAPHORE_STRUCT_SIZE, ONE_WORD));
page_count -= line_count;
src_offset += (PAGE_SIZE * line_count);
......
drivers/gpu/drm/nouveau/nouveau_boa0b5.c
View file @ 6c751372
......@@ -32,6 +32,8 @@
#include <nvif/push906f.h>
#include <nvhw/class/cla0b5.h>
int
nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
......@@ -44,15 +46,32 @@ nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
if (ret)
return ret;
PUSH_NVSQ(push, NVA0B5, 0x0400, upper_32_bits(mem->vma[0].addr),
0x0404, lower_32_bits(mem->vma[0].addr),
0x0408, upper_32_bits(mem->vma[1].addr),
0x040c, lower_32_bits(mem->vma[1].addr),
0x0410, PAGE_SIZE,
0x0414, PAGE_SIZE,
0x0418, PAGE_SIZE,
0x041c, new_reg->num_pages);
PUSH_NVIM(push, NVA0B5, 0x0300, 0x0386);
PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
NVVAL(NVA0B5, OFFSET_IN_UPPER, UPPER, upper_32_bits(mem->vma[0].addr)),
OFFSET_IN_LOWER, lower_32_bits(mem->vma[0].addr),
OFFSET_OUT_UPPER,
NVVAL(NVA0B5, OFFSET_OUT_UPPER, UPPER, upper_32_bits(mem->vma[1].addr)),
OFFSET_OUT_LOWER, lower_32_bits(mem->vma[1].addr),
PITCH_IN, PAGE_SIZE,
PITCH_OUT, PAGE_SIZE,
LINE_LENGTH_IN, PAGE_SIZE,
LINE_COUNT, new_reg->num_pages);
PUSH_IMMD(push, NVA0B5, LAUNCH_DMA,
NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) |
NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) |
NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) |
NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) |
NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |
NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |
NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, TRUE) |
NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) |
NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING) |
NVDEF(NVA0B5, LAUNCH_DMA, SRC_TYPE, VIRTUAL) |
NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, VIRTUAL));
return 0;
}
......
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