Commit 6d04ee9d authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher

drm/amd/display: Restructuring and cleaning up DML

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 19b7fe4a
......@@ -27,20 +27,36 @@
float dcn_bw_mod(const float arg1, const float arg2)
{
if (arg1 != arg1)
return arg2;
if (arg2 != arg2)
return arg1;
return arg1 - arg1 * ((int) (arg1 / arg2));
}
float dcn_bw_min2(const float arg1, const float arg2)
{
if (arg1 != arg1)
return arg2;
if (arg2 != arg2)
return arg1;
return arg1 < arg2 ? arg1 : arg2;
}
unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
{
if (arg1 != arg1)
return arg2;
if (arg2 != arg2)
return arg1;
return arg1 > arg2 ? arg1 : arg2;
}
float dcn_bw_max2(const float arg1, const float arg2)
{
if (arg1 != arg1)
return arg2;
if (arg2 != arg2)
return arg1;
return arg1 > arg2 ? arg1 : arg2;
}
......
......@@ -386,10 +386,6 @@ static void pipe_ctx_to_e2e_pipe_params (
- pipe->stream->timing.v_addressable
- pipe->stream->timing.v_border_bottom
- pipe->stream->timing.v_border_top;
input->dest.vsync_plus_back_porch = pipe->stream->timing.v_total
- pipe->stream->timing.v_addressable
- pipe->stream->timing.v_front_porch;
input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;
input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
......@@ -459,9 +455,9 @@ static void dcn_bw_calc_rq_dlg_ttu(
/*todo: soc->sr_enter_plus_exit_time??*/
dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
dml_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
extract_rq_regs(dml, rq_regs, rq_param);
dml_rq_dlg_get_dlg_params(
dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
dml1_extract_rq_regs(dml, rq_regs, rq_param);
dml1_rq_dlg_get_dlg_params(
dml,
dlg_regs,
ttu_regs,
......@@ -474,96 +470,6 @@ static void dcn_bw_calc_rq_dlg_ttu(
pipe->plane_state->flip_immediate);
}
static void dcn_dml_wm_override(
const struct dcn_bw_internal_vars *v,
struct display_mode_lib *dml,
struct dc_state *context,
const struct resource_pool *pool)
{
int i, in_idx, active_count;
struct _vcs_dpi_display_e2e_pipe_params_st *input = kzalloc(pool->pipe_count * sizeof(struct _vcs_dpi_display_e2e_pipe_params_st),
GFP_KERNEL);
struct wm {
double urgent;
struct _vcs_dpi_cstate_pstate_watermarks_st cpstate;
double pte_meta_urgent;
} a;
for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
if (!pipe->stream || !pipe->plane_state)
continue;
input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk;
input[in_idx].clks_cfg.dispclk_mhz = v->dispclk;
input[in_idx].clks_cfg.dppclk_mhz = v->dppclk;
input[in_idx].clks_cfg.refclk_mhz = pool->ref_clock_inKhz / 1000;
input[in_idx].clks_cfg.socclk_mhz = v->socclk;
input[in_idx].clks_cfg.voltage = v->voltage_level;
input[in_idx].dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
input[in_idx].dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
//input[in_idx].dout.output_standard;
switch (v->output_deep_color[in_idx]) {
case dcn_bw_encoder_12bpc:
input[in_idx].dout.output_bpc = dm_out_12;
break;
case dcn_bw_encoder_10bpc:
input[in_idx].dout.output_bpc = dm_out_10;
break;
case dcn_bw_encoder_8bpc:
default:
input[in_idx].dout.output_bpc = dm_out_8;
break;
}
pipe_ctx_to_e2e_pipe_params(pipe, &input[in_idx].pipe);
dml_rq_dlg_get_rq_reg(
dml,
&pipe->rq_regs,
input[in_idx].pipe.src);
in_idx++;
}
active_count = in_idx;
a.urgent = dml_wm_urgent_e2e(dml, input, active_count);
a.cpstate = dml_wm_cstate_pstate_e2e(dml, input, active_count);
a.pte_meta_urgent = dml_wm_pte_meta_urgent(dml, a.urgent);
context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
a.cpstate.cstate_exit_us * 1000;
context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
a.cpstate.cstate_enter_plus_exit_us * 1000;
context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
a.cpstate.pstate_change_us * 1000;
context->bw.dcn.watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;
context->bw.dcn.watermarks.a.urgent_ns = a.urgent * 1000;
context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
if (!pipe->stream || !pipe->plane_state)
continue;
dml_rq_dlg_get_dlg_reg(dml,
&pipe->dlg_regs,
&pipe->ttu_regs,
input, active_count,
in_idx,
true,
true,
v->pte_enable == dcn_bw_yes,
pipe->plane_state->flip_immediate);
in_idx++;
}
kfree(input);
}
static void split_stream_across_pipes(
struct resource_context *res_ctx,
const struct resource_pool *pool,
......@@ -1163,9 +1069,6 @@ bool dcn_validate_bandwidth(
input_idx++;
}
if (dc->debug.use_dml_wm)
dcn_dml_wm_override(v, (struct display_mode_lib *)
&dc->dml, context, pool);
}
if (v->voltage_level == 0) {
......
......@@ -200,7 +200,6 @@ struct dc_debug {
bool disable_hubp_power_gate;
bool disable_pplib_wm_range;
enum wm_report_mode pplib_wm_report_mode;
bool use_dml_wm;
unsigned int min_disp_clk_khz;
int sr_exit_time_dpm0_ns;
int sr_enter_plus_exit_time_dpm0_ns;
......
......@@ -425,8 +425,6 @@ static const struct dc_debug debug_defaults_drv = {
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = false,
.pplib_wm_report_mode = WM_REPORT_DEFAULT,
.use_dml_wm = false,
.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
.disable_dcc = DCC_ENABLE,
.voltage_align_fclk = true,
......@@ -439,8 +437,7 @@ static const struct dc_debug debug_defaults_diags = {
.clock_trace = true,
.disable_stutter = true,
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = true,
.use_dml_wm = false,
.disable_pplib_wm_range = true
};
static void dcn10_dpp_destroy(struct transform **xfm)
......
......@@ -3,19 +3,19 @@
# It provides the general basic services required by other DAL
# subcomponents.
CFLAGS_display_mode_vba.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_display_mode_lib.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_display_pipe_clocks.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_dml1_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_display_rq_dlg_helpers.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_display_watermark.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_soc_bounding_box.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_dml_common_defs.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_display_mode_support.o := -mhard-float -msse -mpreferred-stack-boundary=4
DML = display_mode_lib.o display_pipe_clocks.o display_rq_dlg_calc.o \
display_rq_dlg_helpers.o display_watermark.o \
soc_bounding_box.o dml_common_defs.o display_mode_support.o
display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
soc_bounding_box.o dml_common_defs.o display_mode_vba.o
AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
......
......@@ -25,9 +25,11 @@
#ifndef __DC_FEATURES_H__
#define __DC_FEATURES_H__
// local features
#define DC__PRESENT 1
#define DC__PRESENT__1 1
#define DC__NUM_DPP 4
#define DC__VOLTAGE_STATES 7
#define DC__NUM_DPP__4 1
#define DC__NUM_DPP__0_PRESENT 1
#define DC__NUM_DPP__1_PRESENT 1
......
......@@ -24,14 +24,12 @@
*/
#ifndef __DISPLAY_MODE_ENUMS_H__
#define __DISPLAY_MODE_ENUMS_H__
enum output_encoder_class {
dm_dp = 0,
dm_hdmi = 1,
dm_wb = 2
dm_dp = 0, dm_hdmi = 1, dm_wb = 2
};
enum output_format_class {
dm_444 = 0,
dm_420 = 1
dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
};
enum source_format_class {
dm_444_16 = 0,
......@@ -40,18 +38,14 @@ enum source_format_class {
dm_420_8 = 3,
dm_420_10 = 4,
dm_422_8 = 5,
dm_422_10 = 6
dm_422_10 = 6,
dm_444_8 = 7
};
enum output_bpc_class {
dm_out_6 = 0,
dm_out_8 = 1,
dm_out_10 = 2,
dm_out_12 = 3,
dm_out_16 = 4
dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
};
enum scan_direction_class {
dm_horz = 0,
dm_vert = 1
dm_horz = 0, dm_vert = 1
};
enum dm_swizzle_mode {
dm_sw_linear = 0,
......@@ -84,28 +78,30 @@ enum dm_swizzle_mode {
dm_sw_SPARE_14 = 27,
dm_sw_SPARE_15 = 28,
dm_sw_var_s_x = 29,
dm_sw_var_d_x = 30
dm_sw_var_d_x = 30,
dm_sw_64kb_r_x
};
enum lb_depth {
dm_lb_10 = 30,
dm_lb_8 = 24,
dm_lb_6 = 18,
dm_lb_12 = 36
dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16
};
enum voltage_state {
dm_vmin = 0,
dm_vmid = 1,
dm_vnom = 2,
dm_vmax = 3,
dm_vmax_exceeded = 4
dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
};
enum source_macro_tile_size {
dm_4k_tile = 0,
dm_64k_tile = 1,
dm_256k_tile = 2
dm_4k_tile = 0, dm_64k_tile = 1, dm_256k_tile = 2
};
enum cursor_bpp {
dm_cur_2bit = 0,
dm_cur_32bit = 1
dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
};
enum clock_change_support {
dm_dram_clock_change_uninitialized = 0,
dm_dram_clock_change_vactive,
dm_dram_clock_change_vblank,
dm_dram_clock_change_unsupported
};
enum output_standard {
dm_std_uninitialized = 0, dm_std_cvtr2, dm_std_cvt
};
#endif
......@@ -24,6 +24,7 @@
*/
#include "display_mode_lib.h"
#include "dc_features.h"
static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)
{
......@@ -128,11 +129,7 @@ static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project pro
static void set_mode_evaluation(struct _vcs_dpi_mode_evaluation_st *me, enum dml_project project)
{
if (project == DML_PROJECT_RAVEN1) {
me->voltage_override = dm_vmin;
} else {
BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
}
me->voltage_override = dm_vmin;
}
void dml_init_instance(struct display_mode_lib *lib, enum dml_project project)
......
......@@ -25,12 +25,13 @@
#ifndef __DISPLAY_MODE_LIB_H__
#define __DISPLAY_MODE_LIB_H__
#include "dml_common_defs.h"
#include "soc_bounding_box.h"
#include "display_watermark.h"
#include "display_mode_vba.h"
#include "display_pipe_clocks.h"
#include "display_rq_dlg_calc.h"
#include "display_mode_support.h"
#include "dml1_display_rq_dlg_calc.h"
enum dml_project {
DML_PROJECT_UNDEFINED,
......@@ -42,8 +43,7 @@ struct display_mode_lib {
struct _vcs_dpi_soc_bounding_box_st soc;
struct _vcs_dpi_mode_evaluation_st me;
enum dml_project project;
struct dml_ms_internal_vars vars;
struct _vcs_dpi_wm_calc_pipe_params_st wm_param[DC__NUM_PIPES__MAX];
struct vba_vars_st vba;
struct dal_logger *logger;
};
......
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DISPLAY_MODE_SUPPORT_H__
#define __DISPLAY_MODE_SUPPORT_H__
#include "dml_common_defs.h"
struct display_mode_lib;
#define NumberOfStates 4
#define NumberOfStatesPlusTwo (NumberOfStates+2)
struct dml_ms_internal_vars {
double ScaleRatioSupport;
double SourceFormatPixelAndScanSupport;
double TotalReadBandwidthConsumedGBytePerSecond;
double TotalWriteBandwidthConsumedGBytePerSecond;
double TotalBandwidthConsumedGBytePerSecond;
double DCCEnabledInAnyPlane;
double ReturnBWToDCNPerState;
double CriticalPoint;
double WritebackLatencySupport;
double RequiredOutputBW;
double TotalNumberOfActiveWriteback;
double TotalAvailableWritebackSupport;
double MaximumSwathWidth;
double NumberOfDPPRequiredForDETSize;
double NumberOfDPPRequiredForLBSize;
double MinDispclkUsingSingleDPP;
double MinDispclkUsingDualDPP;
double ViewportSizeSupport;
double SwathWidthGranularityY;
double RoundedUpMaxSwathSizeBytesY;
double SwathWidthGranularityC;
double RoundedUpMaxSwathSizeBytesC;
double LinesInDETLuma;
double LinesInDETChroma;
double EffectiveLBLatencyHidingSourceLinesLuma;
double EffectiveLBLatencyHidingSourceLinesChroma;
double EffectiveDETLBLinesLuma;
double EffectiveDETLBLinesChroma;
double ProjectedDCFCLKDeepSleep;
double MetaReqHeightY;
double MetaReqWidthY;
double MetaSurfaceWidthY;
double MetaSurfaceHeightY;
double MetaPteBytesPerFrameY;
double MetaRowBytesY;
double MacroTileBlockSizeBytesY;
double MacroTileBlockHeightY;
double DataPTEReqHeightY;
double DataPTEReqWidthY;
double DPTEBytesPerRowY;
double MetaReqHeightC;
double MetaReqWidthC;
double MetaSurfaceWidthC;
double MetaSurfaceHeightC;
double MetaPteBytesPerFrameC;
double MetaRowBytesC;
double MacroTileBlockSizeBytesC;
double MacroTileBlockHeightC;
double MacroTileBlockWidthC;
double DataPTEReqHeightC;
double DataPTEReqWidthC;
double DPTEBytesPerRowC;
double VInitY;
double MaxPartialSwY;
double VInitC;
double MaxPartialSwC;
double dst_x_after_scaler;
double dst_y_after_scaler;
double TimeCalc;
double VUpdateOffset;
double TotalRepeaterDelay;
double VUpdateWidth;
double VReadyOffset;
double TimeSetup;
double ExtraLatency;
double MaximumVStartup;
double BWAvailableForImmediateFlip;
double TotalImmediateFlipBytes;
double TimeForMetaPTEWithImmediateFlip;
double TimeForMetaPTEWithoutImmediateFlip;
double TimeForMetaAndDPTERowWithImmediateFlip;
double TimeForMetaAndDPTERowWithoutImmediateFlip;
double LineTimesToRequestPrefetchPixelDataWithImmediateFlip;
double LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip;
double MaximumReadBandwidthWithPrefetchWithImmediateFlip;
double MaximumReadBandwidthWithPrefetchWithoutImmediateFlip;
double VoltageOverrideLevel;
double VoltageLevelWithImmediateFlip;
double VoltageLevelWithoutImmediateFlip;
double ImmediateFlipSupported;
double VoltageLevel;
double DCFCLK;
double FabricAndDRAMBandwidth;
double SwathWidthYSingleDPP[DC__NUM_PIPES__MAX];
double BytePerPixelInDETY[DC__NUM_PIPES__MAX];
double BytePerPixelInDETC[DC__NUM_PIPES__MAX];
double ReadBandwidth[DC__NUM_PIPES__MAX];
double WriteBandwidth[DC__NUM_PIPES__MAX];
double DCFCLKPerState[NumberOfStatesPlusTwo];
double FabricAndDRAMBandwidthPerState[NumberOfStatesPlusTwo];
double ReturnBWPerState[NumberOfStatesPlusTwo];
double BandwidthSupport[NumberOfStatesPlusTwo];
double UrgentRoundTripAndOutOfOrderLatencyPerState[NumberOfStatesPlusTwo];
double ROBSupport[NumberOfStatesPlusTwo];
double RequiredPHYCLK[DC__NUM_PIPES__MAX];
double DIOSupport[NumberOfStatesPlusTwo];
double PHYCLKPerState[NumberOfStatesPlusTwo];
double PSCL_FACTOR[DC__NUM_PIPES__MAX];
double PSCL_FACTOR_CHROMA[DC__NUM_PIPES__MAX];
double MinDPPCLKUsingSingleDPP[DC__NUM_PIPES__MAX];
double Read256BlockHeightY[DC__NUM_PIPES__MAX];
double Read256BlockWidthY[DC__NUM_PIPES__MAX];
double Read256BlockHeightC[DC__NUM_PIPES__MAX];
double Read256BlockWidthC[DC__NUM_PIPES__MAX];
double MaxSwathHeightY[DC__NUM_PIPES__MAX];
double MaxSwathHeightC[DC__NUM_PIPES__MAX];
double MinSwathHeightY[DC__NUM_PIPES__MAX];
double MinSwathHeightC[DC__NUM_PIPES__MAX];
double NumberOfDPPRequiredForDETAndLBSize[DC__NUM_PIPES__MAX];
double TotalNumberOfActiveDPP[NumberOfStatesPlusTwo * 2];
double RequiredDISPCLK[NumberOfStatesPlusTwo * 2];
double DISPCLK_DPPCLK_Support[NumberOfStatesPlusTwo * 2];
double MaxDispclk[NumberOfStatesPlusTwo];
double MaxDppclk[NumberOfStatesPlusTwo];
double NoOfDPP[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
double TotalAvailablePipesSupport[NumberOfStatesPlusTwo * 2];
double SwathWidthYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
double SwathHeightYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
double SwathHeightCPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
double DETBufferSizeYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
double UrgentLatencySupportUsPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
double UrgentLatencySupport[NumberOfStatesPlusTwo * 2];
double TotalNumberOfDCCActiveDPP[NumberOfStatesPlusTwo * 2];
double DPTEBytesPerRow[DC__NUM_PIPES__MAX];
double MetaPTEBytesPerFrame[DC__NUM_PIPES__MAX];
double MetaRowBytes[DC__NUM_PIPES__MAX];
double PrefillY[DC__NUM_PIPES__MAX];
double MaxNumSwY[DC__NUM_PIPES__MAX];
double PrefetchLinesY[DC__NUM_PIPES__MAX];
double PrefillC[DC__NUM_PIPES__MAX];
double MaxNumSwC[DC__NUM_PIPES__MAX];
double PrefetchLinesC[DC__NUM_PIPES__MAX];
double LineTimesForPrefetch[DC__NUM_PIPES__MAX];
double PrefetchBW[DC__NUM_PIPES__MAX];
double LinesForMetaPTEWithImmediateFlip[DC__NUM_PIPES__MAX];
double LinesForMetaPTEWithoutImmediateFlip[DC__NUM_PIPES__MAX];
double LinesForMetaAndDPTERowWithImmediateFlip[DC__NUM_PIPES__MAX];
double LinesForMetaAndDPTERowWithoutImmediateFlip[DC__NUM_PIPES__MAX];
double VRatioPreYWithImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
double VRatioPreCWithImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
double RequiredPrefetchPixelDataBWWithImmediateFlip[NumberOfStatesPlusTwo * 2
* DC__NUM_PIPES__MAX];
double VRatioPreYWithoutImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
double VRatioPreCWithoutImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
double RequiredPrefetchPixelDataBWWithoutImmediateFlip[NumberOfStatesPlusTwo * 2
* DC__NUM_PIPES__MAX];
double PrefetchSupportedWithImmediateFlip[NumberOfStatesPlusTwo * 2];
double PrefetchSupportedWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
double VRatioInPrefetchSupportedWithImmediateFlip[NumberOfStatesPlusTwo * 2];
double VRatioInPrefetchSupportedWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
double ModeSupportWithImmediateFlip[NumberOfStatesPlusTwo * 2];
double ModeSupportWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
double RequiredDISPCLKPerRatio[2];
double DPPPerPlanePerRatio[2 * DC__NUM_PIPES__MAX];
double DISPCLK_DPPCLK_SupportPerRatio[2];
struct _vcs_dpi_wm_calc_pipe_params_st planes[DC__NUM_PIPES__MAX];
};
int dml_ms_check(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
int num_pipes);
#endif
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This diff is collapsed.
......@@ -29,13 +29,9 @@
struct display_mode_lib;
struct _vcs_dpi_display_pipe_clock_st dml_clks_get_pipe_clocks(
display_pipe_clock_st dml_clks_get_pipe_clocks(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
display_e2e_pipe_params_st *e2e,
unsigned int num_pipes);
bool dml_clks_pipe_clock_requirement_fit_power_constraint(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
unsigned int num_dpp_in_grp);
#endif
......@@ -22,103 +22,114 @@
* Authors: AMD
*
*/
#ifndef __DISPLAY_RQ_DLG_CALC_H__
#define __DISPLAY_RQ_DLG_CALC_H__
#ifndef __DML2_DISPLAY_RQ_DLG_CALC_H__
#define __DML2_DISPLAY_RQ_DLG_CALC_H__
#include "dml_common_defs.h"
#include "display_rq_dlg_helpers.h"
struct display_mode_lib;
void extract_rq_regs(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_rq_regs_st *rq_regs,
const struct _vcs_dpi_display_rq_params_st rq_param);
/* Function: dml_rq_dlg_get_rq_params
* Calculate requestor related parameters that register definition agnostic
* (i.e. this layer does try to separate real values from register defintion)
* Input:
* pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
* Output:
* rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
*/
// Function: dml_rq_dlg_get_rq_params
// Calculate requestor related parameters that register definition agnostic
// (i.e. this layer does try to separate real values from register definition)
// Input:
// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
// Output:
// rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
//
void dml_rq_dlg_get_rq_params(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_rq_params_st *rq_param,
const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
display_rq_params_st *rq_param,
const display_pipe_source_params_st pipe_src_param);
/* Function: dml_rq_dlg_get_rq_reg
* Main entry point for test to get the register values out of this DML class.
* This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
* and then populate the rq_regs struct
* Input:
* pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
* Output:
* rq_regs - struct that holds all the RQ registers field value.
* See also: <display_rq_regs_st>
*/
// Function: dml_rq_dlg_get_rq_reg
// Main entry point for test to get the register values out of this DML class.
// This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
// and then populate the rq_regs struct
// Input:
// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
// Output:
// rq_regs - struct that holds all the RQ registers field value.
// See also: <display_rq_regs_st>
void dml_rq_dlg_get_rq_reg(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_rq_regs_st *rq_regs,
const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
display_rq_regs_st *rq_regs,
const display_pipe_source_params_st pipe_src_param);
/* Function: dml_rq_dlg_get_dlg_params
* Calculate deadline related parameters
*/
void dml_rq_dlg_get_dlg_params(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
// Function: dml_rq_dlg_get_dlg_params
// Calculate deadline related parameters
//
void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *e2e_pipe_param,
const unsigned int num_pipes,
const unsigned int pipe_idx,
display_dlg_regs_st *disp_dlg_regs,
display_ttu_regs_st *disp_ttu_regs,
const display_rq_dlg_params_st rq_dlg_param,
const display_dlg_sys_params_st dlg_sys_param,
const bool cstate_en,
const bool pstate_en,
const bool vm_en,
const bool iflip_en);
const bool ignore_viewport_pos,
const bool immediate_flip_support);
/* Function: dml_rq_dlg_get_dlg_param_prefetch
* For flip_bw programming guide change, now dml needs to calculate the flip_bytes and prefetch_bw
* for ALL pipes and use this info to calculate the prefetch programming.
* Output: prefetch_param.prefetch_bw and flip_bytes
*/
// Function: dml_rq_dlg_get_dlg_param_prefetch
// For flip_bw programming guide change, now dml needs to calculate the flip_bytes and prefetch_bw
// for ALL pipes and use this info to calculate the prefetch programming.
// Output: prefetch_param.prefetch_bw and flip_bytes
void dml_rq_dlg_get_dlg_params_prefetch(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_dlg_prefetch_param_st *prefetch_param,
struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
display_dlg_prefetch_param_st *prefetch_param,
display_rq_dlg_params_st rq_dlg_param,
display_dlg_sys_params_st dlg_sys_param,
display_e2e_pipe_params_st e2e_pipe_param,
const bool cstate_en,
const bool pstate_en,
const bool vm_en);
/* Function: dml_rq_dlg_get_dlg_reg
* Calculate and return DLG and TTU register struct given the system setting
* Output:
* dlg_regs - output DLG register struct
* ttu_regs - output DLG TTU register struct
* Input:
* e2e_pipe_param - "compacted" array of e2e pipe param struct
* num_pipes - num of active "pipe" or "route"
* pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
* cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
* Added for legacy or unrealistic timing tests.
*/
// Function: dml_rq_dlg_get_dlg_reg
// Calculate and return DLG and TTU register struct given the system setting
// Output:
// dlg_regs - output DLG register struct
// ttu_regs - output DLG TTU register struct
// Input:
// e2e_pipe_param - "compacted" array of e2e pipe param struct
// num_pipes - num of active "pipe" or "route"
// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
// cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
// Added for legacy or unrealistic timing tests.
void dml_rq_dlg_get_dlg_reg(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param,
display_dlg_regs_st *dlg_regs,
display_ttu_regs_st *ttu_regs,
display_e2e_pipe_params_st *e2e_pipe_param,
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
const bool pstate_en,
const bool vm_en,
const bool iflip_en);
const bool ignore_viewport_pos,
const bool immediate_flip_support);
/* Function: dml_rq_dlg_get_row_heights
* Calculate dpte and meta row heights
*/
// Function: dml_rq_dlg_get_calculated_vstartup
// Calculate and return vstartup
// Output:
// unsigned int vstartup
// Input:
// e2e_pipe_param - "compacted" array of e2e pipe param struct
// num_pipes - num of active "pipe" or "route"
// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
// NOTE: this MUST be called after setting the prefetch mode!
unsigned int dml_rq_dlg_get_calculated_vstartup(
struct display_mode_lib *mode_lib,
display_e2e_pipe_params_st *e2e_pipe_param,
const unsigned int num_pipes,
const unsigned int pipe_idx);
// Function: dml_rq_dlg_get_row_heights
// Calculate dpte and meta row heights
void dml_rq_dlg_get_row_heights(
struct display_mode_lib *mode_lib,
unsigned int *o_dpte_row_height,
......@@ -131,9 +142,7 @@ void dml_rq_dlg_get_row_heights(
int source_scan,
int is_chroma);
/* Function: dml_rq_dlg_get_arb_params */
void dml_rq_dlg_get_arb_params(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_arb_params_st *arb_param);
// Function: dml_rq_dlg_get_arb_params
void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param);
#endif
......@@ -22,6 +22,7 @@
* Authors: AMD
*
*/
#ifndef __DISPLAY_RQ_DLG_HELPERS_H__
#define __DISPLAY_RQ_DLG_HELPERS_H__
......@@ -31,36 +32,16 @@
/* Function: Printer functions
* Print various struct
*/
void print__rq_params_st(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_rq_params_st rq_param);
void print__data_rq_sizing_params_st(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_data_rq_sizing_params_st rq_sizing);
void print__data_rq_dlg_params_st(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_data_rq_dlg_params_st rq_dlg_param);
void print__data_rq_misc_params_st(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_data_rq_misc_params_st rq_misc_param);
void print__rq_dlg_params_st(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param);
void print__dlg_sys_params_st(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param);
void print__rq_params_st(struct display_mode_lib *mode_lib, display_rq_params_st rq_param);
void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, display_data_rq_sizing_params_st rq_sizing);
void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st rq_dlg_param);
void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, display_data_rq_misc_params_st rq_misc_param);
void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, display_rq_dlg_params_st rq_dlg_param);
void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, display_dlg_sys_params_st dlg_sys_param);
void print__data_rq_regs_st(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_data_rq_regs_st data_rq_regs);
void print__rq_regs_st(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_rq_regs_st rq_regs);
void print__dlg_regs_st(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_dlg_regs_st dlg_regs);
void print__ttu_regs_st(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_ttu_regs_st ttu_regs);
void print__data_rq_regs_st(struct display_mode_lib *mode_lib, display_data_rq_regs_st data_rq_regs);
void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs);
void print__dlg_regs_st(struct display_mode_lib *mode_lib, display_dlg_regs_st dlg_regs);
void print__ttu_regs_st(struct display_mode_lib *mode_lib, display_ttu_regs_st ttu_regs);
#endif
This diff is collapsed.
This diff is collapsed.
......@@ -22,77 +22,46 @@
* Authors: AMD
*
*/
#ifndef __DISPLAY_WATERMARK_H__
#define __DISPLAY_WATERMARK_H__
#ifndef __DISPLAY_RQ_DLG_CALC_H__
#define __DISPLAY_RQ_DLG_CALC_H__
#include "dml_common_defs.h"
#include "display_rq_dlg_helpers.h"
struct display_mode_lib;
double dml_wm_urgent_extra(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
unsigned int num_pipes);
double dml_wm_urgent_extra_max(struct display_mode_lib *mode_lib);
double dml_wm_urgent_e2e(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
unsigned int num_pipes);
double dml_wm_urgent(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_wm_calc_pipe_params_st *planes,
unsigned int num_planes);
double dml_wm_pte_meta_urgent(struct display_mode_lib *mode_lib, double urgent_wm_us);
double dml_wm_dcfclk_deepsleep_mhz_e2e(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
unsigned int num_pipes);
double dml_wm_dcfclk_deepsleep_mhz(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_wm_calc_pipe_params_st *planes,
unsigned int num_planes);
struct _vcs_dpi_cstate_pstate_watermarks_st dml_wm_cstate_pstate_e2e(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
unsigned int num_pipes);
struct _vcs_dpi_cstate_pstate_watermarks_st dml_wm_cstate_pstate(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
unsigned int num_pipes);
double dml_wm_writeback_pstate_e2e(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
unsigned int num_pipes);
double dml_wm_writeback_pstate(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
unsigned int num_pipes);
double dml_wm_expected_stutter_eff_e2e(
void dml1_extract_rq_regs(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
unsigned int num_pipes);
double dml_wm_expected_stutter_eff_e2e_with_vblank(
struct _vcs_dpi_display_rq_regs_st *rq_regs,
const struct _vcs_dpi_display_rq_params_st rq_param);
/* Function: dml_rq_dlg_get_rq_params
* Calculate requestor related parameters that register definition agnostic
* (i.e. this layer does try to separate real values from register definition)
* Input:
* pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
* Output:
* rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
*/
void dml1_rq_dlg_get_rq_params(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
unsigned int num_pipes);
struct _vcs_dpi_display_rq_params_st *rq_param,
const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
unsigned int dml_wm_e2e_to_wm(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
unsigned int num_pipes,
struct _vcs_dpi_wm_calc_pipe_params_st *wm);
double dml_wm_calc_total_data_read_bw(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_wm_calc_pipe_params_st *planes,
unsigned int num_planes);
double dml_wm_calc_return_bw(
/* Function: dml_rq_dlg_get_dlg_params
* Calculate deadline related parameters
*/
void dml1_rq_dlg_get_dlg_params(
struct display_mode_lib *mode_lib,
struct _vcs_dpi_wm_calc_pipe_params_st *planes,
unsigned int num_planes);
struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
const bool cstate_en,
const bool pstate_en,
const bool vm_en,
const bool iflip_en);
#endif
......@@ -36,21 +36,21 @@ double dml_max(double a, double b)
return (double) dcn_bw_max2(a, b);
}
double dml_ceil(double a)
double dml_ceil(double a, double granularity)
{
return (double) dcn_bw_ceil2(a, 1);
return (double) dcn_bw_ceil2(a, granularity);
}
double dml_floor(double a)
double dml_floor(double a, double granularity)
{
return (double) dcn_bw_floor2(a, 1);
return (double) dcn_bw_floor2(a, granularity);
}
double dml_round(double a)
{
double round_pt = 0.5;
double ceil = dml_ceil(a);
double floor = dml_floor(a);
double ceil = dml_ceil(a, 1);
double floor = dml_floor(a, 1);
if (a - floor >= round_pt)
return ceil;
......
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