Commit 6e12a52c authored by Jamie Gibbons's avatar Jamie Gibbons Committed by Bartosz Golaszewski

dt-bindings: gpio: mpfs: add coreGPIO support

The GPIO controllers on PolarFire SoC were based on the "soft" IP
CoreGPIO, but the inp/outp registers are at different offsets. Add
compatible to allow for support of both sets of offsets. The soft
core will not always have interrupts wired up, so only enforce them for
the "hard" core on PolarFire SoC.
Signed-off-by: default avatarJamie Gibbons <jamie.gibbons@microchip.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarBartosz Golaszewski <bartosz.golaszewski@linaro.org>
parent 4cece764
......@@ -14,6 +14,7 @@ properties:
items:
- enum:
- microchip,mpfs-gpio
- microchip,coregpio-rtl-v3
reg:
maxItems: 1
......@@ -62,12 +63,21 @@ patternProperties:
- gpio-hog
- gpios
allOf:
- if:
properties:
compatible:
contains:
const: microchip,mpfs-gpio
then:
required:
- interrupts
- "#interrupt-cells"
- interrupt-controller
required:
- compatible
- reg
- interrupts
- "#interrupt-cells"
- interrupt-controller
- "#gpio-cells"
- gpio-controller
- clocks
......
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