Commit 6f3508f6 authored by Dan Carpenter's avatar Dan Carpenter Committed by Borislav Petkov

EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()

dct_sel_base_off is declared as a u64 but we're only using the lower 32
bits because of a shift wrapping bug. This can possibly truncate the
upper 16 bits of DctSelBaseOffset[47:26], causing us to misdecode the CS
row.

Fixes: c8e518d5 ('amd64_edac: Sanitize f10_get_base_addr_offset')
Signed-off-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: <stable@vger.kernel.org>
Link: http://lkml.kernel.org/r/20160120095451.GB19898@mwandaSigned-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 92e963f5
...@@ -1452,7 +1452,7 @@ static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, ...@@ -1452,7 +1452,7 @@ static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
u64 chan_off; u64 chan_off;
u64 dram_base = get_dram_base(pvt, range); u64 dram_base = get_dram_base(pvt, range);
u64 hole_off = f10_dhar_offset(pvt); u64 hole_off = f10_dhar_offset(pvt);
u64 dct_sel_base_off = (pvt->dct_sel_hi & 0xFFFFFC00) << 16; u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;
if (hi_rng) { if (hi_rng) {
/* /*
......
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