Commit 6f4dc24a authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher

drm/amd/powerplay: not use module parameter in powerplay.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1c863802
...@@ -66,6 +66,7 @@ int hwmgr_early_init(struct pp_instance *handle) ...@@ -66,6 +66,7 @@ int hwmgr_early_init(struct pp_instance *handle)
hwmgr->device = handle->device; hwmgr->device = handle->device;
hwmgr->chip_family = handle->chip_family; hwmgr->chip_family = handle->chip_family;
hwmgr->chip_id = handle->chip_id; hwmgr->chip_id = handle->chip_id;
hwmgr->feature_mask = handle->feature_mask;
hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
hwmgr->power_source = PP_PowerSource_AC; hwmgr->power_source = PP_PowerSource_AC;
hwmgr->pp_table_version = PP_TABLE_V1; hwmgr->pp_table_version = PP_TABLE_V1;
...@@ -738,14 +739,14 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr) ...@@ -738,14 +739,14 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
{ {
if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK) if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep); PHM_PlatformCaps_SclkDeepSleep);
else else
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep); PHM_PlatformCaps_SclkDeepSleep);
if (amdgpu_pp_feature_mask & PP_POWER_CONTAINMENT_MASK) { if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
phm_cap_set(hwmgr->platform_descriptor.platformCaps, phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment); PHM_PlatformCaps_PowerContainment);
phm_cap_set(hwmgr->platform_descriptor.platformCaps, phm_cap_set(hwmgr->platform_descriptor.platformCaps,
...@@ -756,7 +757,6 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) ...@@ -756,7 +757,6 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_CAC); PHM_PlatformCaps_CAC);
} }
hwmgr->feature_mask = amdgpu_pp_feature_mask;
return 0; return 0;
} }
......
...@@ -38,8 +38,6 @@ struct pp_hwmgr; ...@@ -38,8 +38,6 @@ struct pp_hwmgr;
struct phm_fan_speed_info; struct phm_fan_speed_info;
struct pp_atomctrl_voltage_table; struct pp_atomctrl_voltage_table;
extern unsigned amdgpu_pp_feature_mask;
#define VOLTAGE_SCALE 4 #define VOLTAGE_SCALE 4
uint8_t convert_to_vid(uint16_t vddc); uint8_t convert_to_vid(uint16_t vddc);
......
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