drm/i915: Collect dbuf device info into a sub-struct

Collect the related dbuf information into a struct.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210416171011.19012-2-ville.syrjala@linux.intel.comReviewed-by: Jani Nikula <jani.nikula@intel.com>

drivers/gpu/drm/i915/display/intel_display_power.c

@@ -4777,7 +4777,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
 			     u8 req_slices)
 {
-	int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+	int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	enum dbuf_slice slice;
 
@@ -4825,7 +4825,7 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
 
 static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
 {
-	const int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+	int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
 	enum dbuf_slice slice;
 
 	for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++)

drivers/gpu/drm/i915/i915_pci.c

@@ -647,8 +647,8 @@ static const struct intel_device_info chv_info = {
 	.has_gt_uc = 1, \
 	.display.has_hdcp = 1, \
 	.display.has_ipc = 1, \
-	.ddb_size = 896, \
-	.num_supported_dbuf_slices = 1
+	.dbuf.size = 896, \
+	.dbuf.num_slices = 1
 
 #define SKL_PLATFORM \
 	GEN9_FEATURES, \
@@ -683,7 +683,7 @@ static const struct intel_device_info skl_gt4_info = {
 #define GEN9_LP_FEATURES \
 	GEN(9), \
 	.is_lp = 1, \
-	.num_supported_dbuf_slices = 1, \
+	.dbuf.num_slices = 1, \
 	.display.has_hotplug = 1, \
 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -720,14 +720,14 @@ static const struct intel_device_info skl_gt4_info = {
 static const struct intel_device_info bxt_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_BROXTON),
-	.ddb_size = 512,
+	.dbuf.size = 512,
 };
 
 static const struct intel_device_info glk_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_GEMINILAKE),
 	.display.ver = 10,
-	.ddb_size = 1024,
+	.dbuf.size = 1024,
 	GLK_COLORS,
 };
 
@@ -790,7 +790,7 @@ static const struct intel_device_info cml_gt2_info = {
 #define GEN10_FEATURES \
 	GEN9_FEATURES, \
 	GEN(10), \
-	.ddb_size = 1024, \
+	.dbuf.size = 1024, \
 	.display.has_dsc = 1, \
 	.has_coherent_ggtt = false, \
 	GLK_COLORS
@@ -830,8 +830,8 @@ static const struct intel_device_info cnl_info = {
 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 	}, \
 	GEN(11), \
-	.ddb_size = 2048, \
-	.num_supported_dbuf_slices = 2, \
+	.dbuf.size = 2048, \
+	.dbuf.num_slices = 2, \
 	.has_logical_ring_elsq = 1, \
 	.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
 

drivers/gpu/drm/i915/intel_device_info.h

@@ -196,8 +196,10 @@ struct intel_device_info {
 #undef DEFINE_FLAG
 	} display;
 
-	u16 ddb_size; /* in blocks */
-	u8 num_supported_dbuf_slices; /* number of DBuf slices */
+	struct {
+		u16 size; /* in blocks */
+		u8 num_slices;
+	} dbuf;
 
 	/* Register offsets for the various display pipes and transcoders */
 	int pipe_offsets[I915_MAX_TRANSCODERS];

drivers/gpu/drm/i915/intel_pm.c

@@ -3637,10 +3637,10 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
 {
 	int i;
-	int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+	int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
 	u8 enabled_slices_mask = 0;
 
-	for (i = 0; i < max_slices; i++) {
+	for (i = 0; i < num_slices; i++) {
 		if (intel_uncore_read(&dev_priv->uncore, DBUF_CTL_S(i)) & DBUF_POWER_STATE)
 			enabled_slices_mask |= BIT(i);
 	}
@@ -4030,7 +4030,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 
 static int intel_dbuf_size(struct drm_i915_private *dev_priv)
 {
-	int ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+	int ddb_size = INTEL_INFO(dev_priv)->dbuf.size;
 
 	drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
 
@@ -4043,7 +4043,7 @@ static int intel_dbuf_size(struct drm_i915_private *dev_priv)
 static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
 {
 	return intel_dbuf_size(dev_priv) /
-		INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+		INTEL_INFO(dev_priv)->dbuf.num_slices;
 }
 
 static void
@@ -4070,8 +4070,8 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
 {
 	u32 slice_mask = 0;
 	u16 ddb_size = intel_dbuf_size(dev_priv);
-	u16 num_supported_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
-	u16 slice_size = ddb_size / num_supported_slices;
+	int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
+	u16 slice_size = ddb_size / num_slices;
 	u16 start_slice;
 	u16 end_slice;
 
@@ -5828,7 +5828,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
 			    "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n",
 			    old_dbuf_state->enabled_slices,
 			    new_dbuf_state->enabled_slices,
-			    INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
+			    INTEL_INFO(dev_priv)->dbuf.num_slices);
 	}
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {