Commit 70be2dd8 authored by Wei Wang's avatar Wei Wang Committed by Marcelo Henrique Cerri

x86/kvm: add MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD to kvm

CVE-2017-5753
CVE-2017-5715

Add field to access guest MSR_IA332_SPEC_CTRL and MSR_IA32_PRED_CMD state.
Signed-off-by: default avatarWei Wang <wei.w.wang@intel.com>
Signed-off-by: default avatarTim Chen <tim.c.chen@linux.intel.com>
Signed-off-by: default avatarAndy Whitcroft <apw@canonical.com>
(backported from commit f93ba2a9b5ab2c275e9adc10876cc0425a33eec0)
Signed-off-by: default avatarAndy Whitcroft <apw@canonical.com>
parent 47a07600
...@@ -557,6 +557,8 @@ struct kvm_vcpu_arch { ...@@ -557,6 +557,8 @@ struct kvm_vcpu_arch {
u64 mcg_ctl; u64 mcg_ctl;
u64 *mce_banks; u64 *mce_banks;
u64 spec_ctrl;
/* Cache MMIO info */ /* Cache MMIO info */
u64 mmio_gva; u64 mmio_gva;
unsigned access; unsigned access;
......
...@@ -48,6 +48,7 @@ ...@@ -48,6 +48,7 @@
#include <asm/kexec.h> #include <asm/kexec.h>
#include <asm/apic.h> #include <asm/apic.h>
#include <asm/irq_remapping.h> #include <asm/irq_remapping.h>
#include <asm/microcode.h>
#include "trace.h" #include "trace.h"
#include "pmu.h" #include "pmu.h"
...@@ -2803,6 +2804,9 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) ...@@ -2803,6 +2804,9 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
case MSR_IA32_TSC: case MSR_IA32_TSC:
msr_info->data = guest_read_tsc(vcpu); msr_info->data = guest_read_tsc(vcpu);
break; break;
case MSR_IA32_SPEC_CTRL:
msr_info->data = vcpu->arch.spec_ctrl;
break;
case MSR_IA32_SYSENTER_CS: case MSR_IA32_SYSENTER_CS:
msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
break; break;
...@@ -2902,6 +2906,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) ...@@ -2902,6 +2906,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
case MSR_IA32_TSC: case MSR_IA32_TSC:
kvm_write_tsc(vcpu, msr_info); kvm_write_tsc(vcpu, msr_info);
break; break;
case MSR_IA32_SPEC_CTRL:
vcpu->arch.spec_ctrl = msr_info->data;
break;
case MSR_IA32_CR_PAT: case MSR_IA32_CR_PAT:
if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
...@@ -5680,6 +5687,7 @@ static int handle_rdmsr(struct kvm_vcpu *vcpu) ...@@ -5680,6 +5687,7 @@ static int handle_rdmsr(struct kvm_vcpu *vcpu)
msr_info.index = ecx; msr_info.index = ecx;
msr_info.host_initiated = false; msr_info.host_initiated = false;
if (vmx_get_msr(vcpu, &msr_info)) { if (vmx_get_msr(vcpu, &msr_info)) {
trace_kvm_msr_read_ex(ecx); trace_kvm_msr_read_ex(ecx);
kvm_inject_gp(vcpu, 0); kvm_inject_gp(vcpu, 0);
...@@ -6273,6 +6281,8 @@ static __init int hardware_setup(void) ...@@ -6273,6 +6281,8 @@ static __init int hardware_setup(void)
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
vmx_disable_intercept_for_msr(MSR_IA32_SPEC_CTRL, false);
vmx_disable_intercept_for_msr(MSR_IA32_PRED_CMD, false);
memcpy(vmx_msr_bitmap_legacy_x2apic, memcpy(vmx_msr_bitmap_legacy_x2apic,
vmx_msr_bitmap_legacy, PAGE_SIZE); vmx_msr_bitmap_legacy, PAGE_SIZE);
......
...@@ -960,7 +960,7 @@ static u32 msrs_to_save[] = { ...@@ -960,7 +960,7 @@ static u32 msrs_to_save[] = {
MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
#endif #endif
MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, MSR_IA32_SPEC_CTRL,
}; };
static unsigned num_msrs_to_save; static unsigned num_msrs_to_save;
......
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