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Commit 70db8a62 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Paul Walmsley
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omap4: dpll: Enable auto gate control for all MX postdividers 

Enable hardware gate control for all dpll MX and X2 postdividers.
This requires the allow_idle/deny_idle functions to be
populated for all clock nodes (mx/x2 post dividers) in
clkops.
Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 97f67898
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Showing with 37 additions and 22 deletions
arch/arm/mach-omap2/clock.h
View file @ 70db8a62
...@@ -150,5 +150,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) ...@@ -150,5 +150,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
extern const struct clkops clkops_omap3_noncore_dpll_ops; extern const struct clkops clkops_omap3_noncore_dpll_ops;
extern const struct clkops clkops_omap3_core_dpll_ops; extern const struct clkops clkops_omap3_core_dpll_ops;
extern const struct clkops clkops_omap4_dpllmx_ops;
#endif #endif
arch/arm/mach-omap2/clock44xx_data.c
View file @ 70db8a62
...@@ -278,8 +278,10 @@ static struct clk dpll_abe_ck = { ...@@ -278,8 +278,10 @@ static struct clk dpll_abe_ck = {
static struct clk dpll_abe_x2_ck = { static struct clk dpll_abe_x2_ck = {
.name = "dpll_abe_x2_ck", .name = "dpll_abe_x2_ck",
.parent = &dpll_abe_ck, .parent = &dpll_abe_ck,
.ops = &clkops_null, .flags = CLOCK_CLKOUTX2,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap3_clkoutx2_recalc, .recalc = &omap3_clkoutx2_recalc,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
}; };
static const struct clksel_rate div31_1to31_rates[] = { static const struct clksel_rate div31_1to31_rates[] = {
...@@ -328,7 +330,7 @@ static struct clk dpll_abe_m2x2_ck = { ...@@ -328,7 +330,7 @@ static struct clk dpll_abe_m2x2_ck = {
.clksel = dpll_abe_m2x2_div, .clksel = dpll_abe_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -395,7 +397,7 @@ static struct clk dpll_abe_m3x2_ck = { ...@@ -395,7 +397,7 @@ static struct clk dpll_abe_m3x2_ck = {
.clksel = dpll_abe_m2x2_div, .clksel = dpll_abe_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -450,6 +452,7 @@ static struct clk dpll_core_ck = { ...@@ -450,6 +452,7 @@ static struct clk dpll_core_ck = {
static struct clk dpll_core_x2_ck = { static struct clk dpll_core_x2_ck = {
.name = "dpll_core_x2_ck", .name = "dpll_core_x2_ck",
.parent = &dpll_core_ck, .parent = &dpll_core_ck,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_null, .ops = &clkops_null,
.recalc = &omap3_clkoutx2_recalc, .recalc = &omap3_clkoutx2_recalc,
}; };
...@@ -465,7 +468,7 @@ static struct clk dpll_core_m6x2_ck = { ...@@ -465,7 +468,7 @@ static struct clk dpll_core_m6x2_ck = {
.clksel = dpll_core_m6x2_div, .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -495,7 +498,7 @@ static struct clk dpll_core_m2_ck = { ...@@ -495,7 +498,7 @@ static struct clk dpll_core_m2_ck = {
.clksel = dpll_core_m2_div, .clksel = dpll_core_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -515,7 +518,7 @@ static struct clk dpll_core_m5x2_ck = { ...@@ -515,7 +518,7 @@ static struct clk dpll_core_m5x2_ck = {
.clksel = dpll_core_m6x2_div, .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -581,7 +584,7 @@ static struct clk dpll_core_m4x2_ck = { ...@@ -581,7 +584,7 @@ static struct clk dpll_core_m4x2_ck = {
.clksel = dpll_core_m6x2_div, .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -606,7 +609,7 @@ static struct clk dpll_abe_m2_ck = { ...@@ -606,7 +609,7 @@ static struct clk dpll_abe_m2_ck = {
.clksel = dpll_abe_m2_div, .clksel = dpll_abe_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -632,7 +635,7 @@ static struct clk dpll_core_m7x2_ck = { ...@@ -632,7 +635,7 @@ static struct clk dpll_core_m7x2_ck = {
.clksel = dpll_core_m6x2_div, .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -689,6 +692,7 @@ static struct clk dpll_iva_ck = { ...@@ -689,6 +692,7 @@ static struct clk dpll_iva_ck = {
static struct clk dpll_iva_x2_ck = { static struct clk dpll_iva_x2_ck = {
.name = "dpll_iva_x2_ck", .name = "dpll_iva_x2_ck",
.parent = &dpll_iva_ck, .parent = &dpll_iva_ck,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_null, .ops = &clkops_null,
.recalc = &omap3_clkoutx2_recalc, .recalc = &omap3_clkoutx2_recalc,
}; };
...@@ -704,7 +708,7 @@ static struct clk dpll_iva_m4x2_ck = { ...@@ -704,7 +708,7 @@ static struct clk dpll_iva_m4x2_ck = {
.clksel = dpll_iva_m4x2_div, .clksel = dpll_iva_m4x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -716,7 +720,7 @@ static struct clk dpll_iva_m5x2_ck = { ...@@ -716,7 +720,7 @@ static struct clk dpll_iva_m5x2_ck = {
.clksel = dpll_iva_m4x2_div, .clksel = dpll_iva_m4x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -764,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = { ...@@ -764,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = {
.clksel = dpll_mpu_m2_div, .clksel = dpll_mpu_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -837,7 +841,7 @@ static struct clk dpll_per_m2_ck = { ...@@ -837,7 +841,7 @@ static struct clk dpll_per_m2_ck = {
.clksel = dpll_per_m2_div, .clksel = dpll_per_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -846,8 +850,10 @@ static struct clk dpll_per_m2_ck = { ...@@ -846,8 +850,10 @@ static struct clk dpll_per_m2_ck = {
static struct clk dpll_per_x2_ck = { static struct clk dpll_per_x2_ck = {
.name = "dpll_per_x2_ck", .name = "dpll_per_x2_ck",
.parent = &dpll_per_ck, .parent = &dpll_per_ck,
.ops = &clkops_null, .flags = CLOCK_CLKOUTX2,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap3_clkoutx2_recalc, .recalc = &omap3_clkoutx2_recalc,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
}; };
static const struct clksel dpll_per_m2x2_div[] = { static const struct clksel dpll_per_m2x2_div[] = {
...@@ -861,7 +867,7 @@ static struct clk dpll_per_m2x2_ck = { ...@@ -861,7 +867,7 @@ static struct clk dpll_per_m2x2_ck = {
.clksel = dpll_per_m2x2_div, .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -887,7 +893,7 @@ static struct clk dpll_per_m4x2_ck = { ...@@ -887,7 +893,7 @@ static struct clk dpll_per_m4x2_ck = {
.clksel = dpll_per_m2x2_div, .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -899,7 +905,7 @@ static struct clk dpll_per_m5x2_ck = { ...@@ -899,7 +905,7 @@ static struct clk dpll_per_m5x2_ck = {
.clksel = dpll_per_m2x2_div, .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -911,7 +917,7 @@ static struct clk dpll_per_m6x2_ck = { ...@@ -911,7 +917,7 @@ static struct clk dpll_per_m6x2_ck = {
.clksel = dpll_per_m2x2_div, .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -923,7 +929,7 @@ static struct clk dpll_per_m7x2_ck = { ...@@ -923,7 +929,7 @@ static struct clk dpll_per_m7x2_ck = {
.clksel = dpll_per_m2x2_div, .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -964,6 +970,7 @@ static struct clk dpll_unipro_ck = { ...@@ -964,6 +970,7 @@ static struct clk dpll_unipro_ck = {
static struct clk dpll_unipro_x2_ck = { static struct clk dpll_unipro_x2_ck = {
.name = "dpll_unipro_x2_ck", .name = "dpll_unipro_x2_ck",
.parent = &dpll_unipro_ck, .parent = &dpll_unipro_ck,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_null, .ops = &clkops_null,
.recalc = &omap3_clkoutx2_recalc, .recalc = &omap3_clkoutx2_recalc,
}; };
...@@ -979,7 +986,7 @@ static struct clk dpll_unipro_m2x2_ck = { ...@@ -979,7 +986,7 @@ static struct clk dpll_unipro_m2x2_ck = {
.clksel = dpll_unipro_m2x2_div, .clksel = dpll_unipro_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
...@@ -1028,7 +1035,8 @@ static struct clk dpll_usb_ck = { ...@@ -1028,7 +1035,8 @@ static struct clk dpll_usb_ck = {
static struct clk dpll_usb_clkdcoldo_ck = { static struct clk dpll_usb_clkdcoldo_ck = {
.name = "dpll_usb_clkdcoldo_ck", .name = "dpll_usb_clkdcoldo_ck",
.parent = &dpll_usb_ck, .parent = &dpll_usb_ck,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1043,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = { ...@@ -1043,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = {
.clksel = dpll_usb_m2_div, .clksel = dpll_usb_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
.ops = &clkops_null, .ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate, .set_rate = &omap2_clksel_set_rate,
......
arch/arm/mach-omap2/dpll44xx.c
View file @ 70db8a62
...@@ -76,3 +76,9 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk) ...@@ -76,3 +76,9 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk)
v |= mask; v |= mask;
__raw_writel(v, clk->clksel_reg); __raw_writel(v, clk->clksel_reg);
} }
const struct clkops clkops_omap4_dpllmx_ops = {
.allow_idle = omap4_dpllmx_allow_gatectrl,
.deny_idle = omap4_dpllmx_deny_gatectrl,
};
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