Commit 7214c058 authored by Eric Huang's avatar Eric Huang Committed by Tim Gardner

drm/amd/amdgpu: enable uvd&vce clock gating for Fiji.

BugLink: http://bugs.launchpad.net/bugs/1546572Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: default avatarEric Huang <JinHuiEric.Huang@amd.com>
(cherry picked from commit 0bbb8176)
Signed-off-by: default avatarAlberto Milone <alberto.milone@canonical.com>
Signed-off-by: default avatarTim Gardner <tim.gardner@canonical.com>
parent 35f9e2c2
......@@ -1443,7 +1443,8 @@ static int vi_common_early_init(void *handle)
break;
case CHIP_FIJI:
adev->has_uvd = true;
adev->cg_flags = 0;
adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG |
AMDGPU_CG_SUPPORT_VCE_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x3c;
break;
......
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