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Commit 72680fbe authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-arm64-dt-for-v5.7-tag2' of... 

Merge tag 'renesas-arm64-dt-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM64 DT updates for v5.7 (take two)

  - Thermal support for R-Car M3-W+,
  - Support for the M3ULCB board with R-Car M3-W+,
  - CPUIdle support for R-Car M3-N and E3,
  - Display support for the HiHope RZ/G2M board,
  - A minor fix.

* tag 'renesas-arm64-dt-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: Add HiHope RZ/G2M board with idk-1110wr display
  arm64: dts: renesas: r8a77990: Add CPUIdle support for CA53 cores
  arm64: dts: renesas: r8a77965: Add CPUIdle support for CA57 cores
  arm64: dts: renesas: r8a77961: salvator-xs: Fix memory unit-address
  arm64: dts: renesas: Add support for M3ULCB with R-Car M3-W+
  arm64: dts: renesas: r8a77961: Add thermal nodes

Link: https://lore.kernel.org/r/20200313154304.1636-3-geert+renesas@glider.beSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a68260c0 e30f5680
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arch/arm64/boot/dts/renesas/Makefile
View file @ 72680fbe
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \
......@@ -12,6 +13,7 @@ dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb r8a77951-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x.dtb r8a77960-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb.dtb r8a77960-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb r8a77965-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
......
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts 0 → 100644
View file @ 72680fbe
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M sub board connected to an
* Advantech IDK-1110WR 10.1" LVDS panel
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774a1-hihope-rzg2m-ex.dts"
#include "rzg2-advantech-idk-1110wr-panel.dtsi"
/ {
backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 50000>;
brightness-levels = <0 2 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
};
&gpio1 {
/*
* When GP1_20 is LOW LVDS0 is connected to the LVDS connector
* When GP1_20 is HIGH LVDS0 is connected to the LT8918L
*/
lvds-connector-en-gpio {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds-connector-en-gpio";
};
};
&lvds0 {
status = "okay";
};
&pfc {
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
View file @ 72680fbe
......@@ -19,7 +19,7 @@ memory@48000000 {
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@400000000 {
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
......
arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts 0 → 100644
View file @ 72680fbe
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car
* M3-W+
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77961.dtsi"
#include "ulcb.dtsi"
/ {
model = "Renesas M3ULCB board based on r8a77961";
compatible = "renesas,m3ulcb", "renesas,r8a77961";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
};
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View file @ 72680fbe
......@@ -474,6 +474,20 @@ sysc: system-controller@e6180000 {
#power-domain-cells = <1>;
};
tsc: thermal@e6198000 {
compatible = "renesas,r8a77961-thermal";
reg = <0 0xe6198000 0 0x100>,
<0 0xe61a0000 0 0x100>,
<0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 522>;
#thermal-sensor-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
#interrupt-cells = <2>;
interrupt-controller;
......@@ -870,6 +884,7 @@ rcar_sound,src {
rcar_sound,ssi {
ssi0: ssi-0 { };
ssi1: ssi-1 { };
ssi2: ssi-2 { };
};
};
......@@ -1073,6 +1088,71 @@ prr: chipid@fff00044 {
};
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
sustainable-power = <3874>;
trips {
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal2: sensor-thermal2 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
sustainable-power = <3874>;
trips {
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
sustainable-power = <3874>;
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&a57_0 2 4>;
contribution = <1024>;
};
map1 {
trip = <&target>;
cooling-device = <&a53_0 0 2>;
contribution = <1024>;
};
};
trips {
target: trip-point1 {
temperature = <100000>;
hysteresis = <1000>;
type = "passive";
};
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
......
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View file @ 72680fbe
......@@ -111,6 +111,7 @@ a57_0: cpu@0 {
power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
#cooling-cells = <2>;
dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
......@@ -124,6 +125,7 @@ a57_1: cpu@1 {
power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
};
......@@ -134,6 +136,19 @@ L2_CA57: cache-controller-0 {
cache-unified;
cache-level = <2>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <500>;
min-residency-us = <4000>;
};
};
};
extal_clk: extal {
......
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View file @ 72680fbe
......@@ -88,6 +88,7 @@ a53_0: cpu@0 {
power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
dynamic-power-coefficient = <277>;
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
......@@ -100,6 +101,7 @@ a53_1: cpu@1 {
power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
......@@ -110,6 +112,19 @@ L2_CA53: cache-controller-0 {
cache-unified;
cache-level = <2>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <700>;
exit-latency-us = <700>;
min-residency-us = <5000>;
};
};
};
extal_clk: extal {
......
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