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Commit 72ac50b2 authored by Jakub Kicinski's avatar Jakub Kicinski
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Merge branch 'net-ipa-gsi-register-consolidation' 

Alex Elder says:

====================
net: ipa: GSI register consolidation

This series rearranges and consolidates some GSI register
definitions.  Its general aim is to make things more
consistent, by:
  - Using enumerated types to define the values held in GSI register
    fields
  - Defining field values in "gsi_reg.h", together with the
    definition of the register (and field) that holds them
  - Format enumerated type members consistently, with hexidecimal
    numeric values, and assignments aligned on the same column

There is one checkpatch "CHECK" warning requesting a blank line; I
ignored that because my intention was to group certain definitions.
====================

Link: https://lore.kernel.org/r/20201110215922.23514-1-elder@linaro.orgSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 2f51e575 4730ab1c
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Showing with 93 additions and 91 deletions
drivers/net/ipa/gsi.c
View file @ 72ac50b2
......@@ -109,62 +109,6 @@ struct gsi_event {
u8 chid;
};
/* Hardware values from the error log register error code field */
enum gsi_err_code {
GSI_INVALID_TRE_ERR = 0x1,
GSI_OUT_OF_BUFFERS_ERR = 0x2,
GSI_OUT_OF_RESOURCES_ERR = 0x3,
GSI_UNSUPPORTED_INTER_EE_OP_ERR = 0x4,
GSI_EVT_RING_EMPTY_ERR = 0x5,
GSI_NON_ALLOCATED_EVT_ACCESS_ERR = 0x6,
GSI_HWO_1_ERR = 0x8,
};
/* Hardware values from the error log register error type field */
enum gsi_err_type {
GSI_ERR_TYPE_GLOB = 0x1,
GSI_ERR_TYPE_CHAN = 0x2,
GSI_ERR_TYPE_EVT = 0x3,
};
/* Hardware values used when programming an event ring */
enum gsi_evt_chtype {
GSI_EVT_CHTYPE_MHI_EV = 0x0,
GSI_EVT_CHTYPE_XHCI_EV = 0x1,
GSI_EVT_CHTYPE_GPI_EV = 0x2,
GSI_EVT_CHTYPE_XDCI_EV = 0x3,
};
/* Hardware values used when programming a channel */
enum gsi_channel_protocol {
GSI_CHANNEL_PROTOCOL_MHI = 0x0,
GSI_CHANNEL_PROTOCOL_XHCI = 0x1,
GSI_CHANNEL_PROTOCOL_GPI = 0x2,
GSI_CHANNEL_PROTOCOL_XDCI = 0x3,
};
/* Hardware values representing an event ring immediate command opcode */
enum gsi_evt_cmd_opcode {
GSI_EVT_ALLOCATE = 0x0,
GSI_EVT_RESET = 0x9,
GSI_EVT_DE_ALLOC = 0xa,
};
/* Hardware values representing a generic immediate command opcode */
enum gsi_generic_cmd_opcode {
GSI_GENERIC_HALT_CHANNEL = 0x1,
GSI_GENERIC_ALLOCATE_CHANNEL = 0x2,
};
/* Hardware values representing a channel immediate command opcode */
enum gsi_ch_cmd_opcode {
GSI_CH_ALLOCATE = 0x0,
GSI_CH_START = 0x1,
GSI_CH_STOP = 0x2,
GSI_CH_RESET = 0x9,
GSI_CH_DE_ALLOC = 0xa,
};
/** gsi_channel_scratch_gpi - GPI protocol scratch register
* @max_outstanding_tre:
* Defines the maximum number of TREs allowed in a single transaction
......@@ -305,7 +249,7 @@ static void gsi_irq_enable(struct gsi *gsi)
/* Global interrupts include hardware error reports. Enable
* that so we can at least report the error should it occur.
*/
iowrite32(ERROR_INT_FMASK, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GLOB_EE));
/* General GSI interrupts are reported to all EEs; if they occur
......@@ -313,9 +257,9 @@ static void gsi_irq_enable(struct gsi *gsi)
* also exists, but we don't support that. We want to be notified
* of errors so we can report them, even if they can't be handled.
*/
val = BUS_ERROR_FMASK;
val |= CMD_FIFO_OVRFLOW_FMASK;
val |= MCS_STACK_OVRFLOW_FMASK;
val = BIT(BUS_ERROR);
val |= BIT(CMD_FIFO_OVRFLOW);
val |= BIT(MCS_STACK_OVRFLOW);
iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GENERAL));
}
......@@ -684,7 +628,8 @@ static void gsi_evt_ring_program(struct gsi *gsi, u32 evt_ring_id)
size_t size = evt_ring->ring.count * GSI_RING_ELEMENT_SIZE;
u32 val;
val = u32_encode_bits(GSI_EVT_CHTYPE_GPI_EV, EV_CHTYPE_FMASK);
/* We program all event rings as GPI type/protocol */
val = u32_encode_bits(GSI_CHANNEL_TYPE_GPI, EV_CHTYPE_FMASK);
val |= EV_INTYPE_FMASK;
val |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, EV_ELEMENT_SIZE_FMASK);
iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id));
......@@ -791,8 +736,8 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell)
/* Arbitrarily pick TRE 0 as the first channel element to use */
channel->tre_ring.index = 0;
/* We program all channels to use GPI protocol */
val = u32_encode_bits(GSI_CHANNEL_PROTOCOL_GPI, CHTYPE_PROTOCOL_FMASK);
/* We program all channels as GPI type/protocol */
val = u32_encode_bits(GSI_CHANNEL_TYPE_GPI, CHTYPE_PROTOCOL_FMASK);
if (channel->toward_ipa)
val |= CHTYPE_DIR_FMASK;
val |= u32_encode_bits(channel->evt_ring_id, ERINDEX_FMASK);
......@@ -1067,7 +1012,7 @@ static void gsi_isr_evt_ctrl(struct gsi *gsi)
static void
gsi_isr_glob_chan_err(struct gsi *gsi, u32 err_ee, u32 channel_id, u32 code)
{
if (code == GSI_OUT_OF_RESOURCES_ERR) {
if (code == GSI_OUT_OF_RESOURCES) {
dev_err(gsi->dev, "channel %u out of resources\n", channel_id);
complete(&gsi->channel[channel_id].completion);
return;
......@@ -1082,7 +1027,7 @@ gsi_isr_glob_chan_err(struct gsi *gsi, u32 err_ee, u32 channel_id, u32 code)
static void
gsi_isr_glob_evt_err(struct gsi *gsi, u32 err_ee, u32 evt_ring_id, u32 code)
{
if (code == GSI_OUT_OF_RESOURCES_ERR) {
if (code == GSI_OUT_OF_RESOURCES) {
struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];
u32 channel_id = gsi_channel_id(evt_ring->channel);
......@@ -1132,7 +1077,7 @@ static void gsi_isr_gp_int1(struct gsi *gsi)
val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET);
result = u32_get_bits(val, GENERIC_EE_RESULT_FMASK);
if (result != GENERIC_EE_SUCCESS_FVAL)
if (result != GENERIC_EE_SUCCESS)
dev_err(gsi->dev, "global INT1 generic result %u\n", result);
complete(&gsi->completion);
......@@ -1145,15 +1090,15 @@ static void gsi_isr_glob_ee(struct gsi *gsi)
val = ioread32(gsi->virt + GSI_CNTXT_GLOB_IRQ_STTS_OFFSET);
if (val & ERROR_INT_FMASK)
if (val & BIT(ERROR_INT))
gsi_isr_glob_err(gsi);
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_CLR_OFFSET);
val &= ~ERROR_INT_FMASK;
val &= ~BIT(ERROR_INT);
if (val & GP_INT1_FMASK) {
val ^= GP_INT1_FMASK;
if (val & BIT(GP_INT1)) {
val ^= BIT(GP_INT1);
gsi_isr_gp_int1(gsi);
}
......@@ -1626,7 +1571,7 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
* halt a modem channel) and only from this function. So we
* enable the GP_INT1 IRQ type here while we're expecting it.
*/
val = ERROR_INT_FMASK | GP_INT1_FMASK;
val = BIT(ERROR_INT) | BIT(GP_INT1);
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
/* First zero the result code field */
......@@ -1642,7 +1587,7 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
success = gsi_command(gsi, GSI_GENERIC_CMD_OFFSET, val, completion);
/* Disable the GP_INT1 IRQ type again */
iowrite32(ERROR_INT_FMASK, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
if (success)
return 0;
......
drivers/net/ipa/gsi_reg.h
View file @ 72ac50b2
......@@ -71,6 +71,13 @@
#define ERINDEX_FMASK GENMASK(18, 14)
#define CHSTATE_FMASK GENMASK(23, 20)
#define ELEMENT_SIZE_FMASK GENMASK(31, 24)
/** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */
enum gsi_channel_type {
GSI_CHANNEL_TYPE_MHI = 0x0,
GSI_CHANNEL_TYPE_XHCI = 0x1,
GSI_CHANNEL_TYPE_GPI = 0x2,
GSI_CHANNEL_TYPE_XDCI = 0x3,
};
#define GSI_CH_C_CNTXT_1_OFFSET(ch) \
GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP)
......@@ -128,6 +135,7 @@
#define EV_INTYPE_FMASK GENMASK(16, 16)
#define EV_CHSTATE_FMASK GENMASK(23, 20)
#define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24)
/* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */
#define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \
GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP)
......@@ -215,6 +223,14 @@
(0x0001f008 + 0x4000 * (ee))
#define CH_CHID_FMASK GENMASK(7, 0)
#define CH_OPCODE_FMASK GENMASK(31, 24)
/** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */
enum gsi_ch_cmd_opcode {
GSI_CH_ALLOCATE = 0x0,
GSI_CH_START = 0x1,
GSI_CH_STOP = 0x2,
GSI_CH_RESET = 0x9,
GSI_CH_DE_ALLOC = 0xa,
};
#define GSI_EV_CH_CMD_OFFSET \
GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP)
......@@ -222,6 +238,12 @@
(0x0001f010 + 0x4000 * (ee))
#define EV_CHID_FMASK GENMASK(7, 0)
#define EV_OPCODE_FMASK GENMASK(31, 24)
/** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */
enum gsi_evt_cmd_opcode {
GSI_EVT_ALLOCATE = 0x0,
GSI_EVT_RESET = 0x9,
GSI_EVT_DE_ALLOC = 0xa,
};
#define GSI_GENERIC_CMD_OFFSET \
GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP)
......@@ -230,17 +252,17 @@
#define GENERIC_OPCODE_FMASK GENMASK(4, 0)
#define GENERIC_CHID_FMASK GENMASK(9, 5)
#define GENERIC_EE_FMASK GENMASK(13, 10)
/** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */
enum gsi_generic_cmd_opcode {
GSI_GENERIC_HALT_CHANNEL = 0x1,
GSI_GENERIC_ALLOCATE_CHANNEL = 0x2,
};
#define GSI_GSI_HW_PARAM_2_OFFSET \
GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP)
#define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \
(0x0001f040 + 0x4000 * (ee))
#define IRAM_SIZE_FMASK GENMASK(2, 0)
#define IRAM_SIZE_ONE_KB_FVAL 0
#define IRAM_SIZE_TWO_KB_FVAL 1
/* The next two values are available for IPA v4.0 and above */
#define IRAM_SIZE_TWO_N_HALF_KB_FVAL 2
#define IRAM_SIZE_THREE_KB_FVAL 3
#define NUM_CH_PER_EE_FMASK GENMASK(7, 3)
#define NUM_EV_PER_EE_FMASK GENMASK(12, 8)
#define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13)
......@@ -253,7 +275,16 @@
/* Fields below are present for IPA v4.2 and above */
#define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30)
#define GSI_USE_INTER_EE_FMASK GENMASK(31, 31)
/** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */
enum gsi_iram_size {
IRAM_SIZE_ONE_KB = 0x0,
IRAM_SIZE_TWO_KB = 0x1,
/* The next two values are available for IPA v4.0 and above */
IRAM_SIZE_TWO_N_HALF_KB = 0x2,
IRAM_SIZE_THREE_KB = 0x3,
};
/* IRQ condition for each type is cleared by writing type-specific register */
#define GSI_CNTXT_TYPE_IRQ_OFFSET \
GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \
......@@ -330,11 +361,13 @@ enum gsi_irq_type_id {
GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \
(0x0001f110 + 0x4000 * (ee))
/* The masks below are used for the general IRQ STTS, EN, and CLR registers */
#define ERROR_INT_FMASK GENMASK(0, 0)
#define GP_INT1_FMASK GENMASK(1, 1)
#define GP_INT2_FMASK GENMASK(2, 2)
#define GP_INT3_FMASK GENMASK(3, 3)
/* Values here are bit positions in the GLOB_IRQ_* registers */
enum gsi_global_irq_id {
ERROR_INT = 0x0,
GP_INT1 = 0x1,
GP_INT2 = 0x2,
GP_INT3 = 0x3,
};
#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
......@@ -348,11 +381,13 @@ enum gsi_irq_type_id {
GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \
(0x0001f128 + 0x4000 * (ee))
/* The masks below are used for the general IRQ STTS, EN, and CLR registers */
#define BREAK_POINT_FMASK GENMASK(0, 0)
#define BUS_ERROR_FMASK GENMASK(1, 1)
#define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2)
#define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3)
/* Values here are bit positions in the (general) GSI_IRQ_* registers */
enum gsi_general_id {
BREAK_POINT = 0x0,
BUS_ERROR = 0x1,
CMD_FIFO_OVRFLOW = 0x2,
MCS_STACK_OVRFLOW = 0x3,
};
#define GSI_CNTXT_INTSET_OFFSET \
GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP)
......@@ -371,6 +406,23 @@ enum gsi_irq_type_id {
#define ERR_VIRT_IDX_FMASK GENMASK(23, 19)
#define ERR_TYPE_FMASK GENMASK(27, 24)
#define ERR_EE_FMASK GENMASK(31, 28)
/** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */
enum gsi_err_code {
GSI_INVALID_TRE = 0x1,
GSI_OUT_OF_BUFFERS = 0x2,
GSI_OUT_OF_RESOURCES = 0x3,
GSI_UNSUPPORTED_INTER_EE_OP = 0x4,
GSI_EVT_RING_EMPTY = 0x5,
GSI_NON_ALLOCATED_EVT_ACCESS = 0x6,
/* 7 is not assigned */
GSI_HWO_1 = 0x8,
};
/** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */
enum gsi_err_type {
GSI_ERR_TYPE_GLOB = 0x1,
GSI_ERR_TYPE_CHAN = 0x2,
GSI_ERR_TYPE_EVT = 0x3,
};
#define GSI_ERROR_LOG_CLR_OFFSET \
GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP)
......@@ -383,10 +435,15 @@ enum gsi_irq_type_id {
(0x0001f400 + 0x4000 * (ee))
#define INTER_EE_RESULT_FMASK GENMASK(2, 0)
#define GENERIC_EE_RESULT_FMASK GENMASK(7, 5)
#define GENERIC_EE_SUCCESS_FVAL 1
#define GENERIC_EE_INCORRECT_DIRECTION_FVAL 3
#define GENERIC_EE_INCORRECT_CHANNEL_FVAL 5
#define GENERIC_EE_NO_RESOURCES_FVAL 7
enum gsi_generic_ee_result {
GENERIC_EE_SUCCESS = 0x1,
GENERIC_EE_CHANNEL_NOT_RUNNING = 0x2,
GENERIC_EE_INCORRECT_DIRECTION = 0x3,
GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4,
GENERIC_EE_INCORRECT_CHANNEL = 0x5,
GENERIC_EE_RETRY = 0x6,
GENERIC_EE_NO_RESOURCES = 0x7,
};
#define USB_MAX_PACKET_FMASK GENMASK(15, 15) /* 0: HS; 1: SS */
#define MHI_BASE_CHANNEL_FMASK GENMASK(31, 24)
......
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