Commit 745dfa07 authored by Varadarajan Narayanan's avatar Varadarajan Narayanan Committed by Bjorn Andersson

clk: qcom: gcc-ipq9574: Add USB related clocks

Add the clocks needed for enabling USB in IPQ9574
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarVaradarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/d1c5aa4a8535c645fdb06df62a562918516ba0c6.1686289721.git.quic_varada@quicinc.com
[bjorn: Clock defines split out to separate commit]
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 9e1857ee
......@@ -2004,6 +2004,41 @@ static struct clk_regmap_mux usb0_pipe_clk_src = {
},
};
static struct clk_branch gcc_usb0_pipe_clk = {
.halt_reg = 0x2c054,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x2c054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb0_pipe_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_pipe_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_sleep_clk = {
.halt_reg = 0x2c058,
.clkr = {
.enable_reg = 0x2c058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb0_sleep_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_sleep_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
F(144000, P_XO, 16, 12, 125),
F(400000, P_XO, 12, 1, 5),
......@@ -4003,6 +4038,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
......
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