clk: exynos4: Use mout_mpll_user_* on Exynos4x12

Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of
sclk_mpll as one of their parents.

This patch moves such clocks from common array into SoC-specific arrays
and adjusts their parent lists respectively.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Documentation/devicetree/bindings/clock/exynos4-clock.txt

@@ -42,6 +42,8 @@ Exynos4 SoC and this is specified where applicable.
   aclk100             14
   aclk160             15
   aclk133             16
+  mout_mpll_user_t    17      Exynos4x12
+  mout_mpll_user_c    18      Exynos4x12
 
 
             [Clock Gate for Special Clocks]