Revert "drm/i915/bdw: BDW Software Turbo"

This reverts commit c76bb61a.

It's apparently too broken so that Rodrigo submitted a patch to add a
config option for it. Given that the design is also ... suboptimal and
that I've only merged this to get lead engineers and managers off my
back for one second let's just revert this.

/me puts on combat gear again

It was worth a shot ...

References: http://mid.mail-archive.com/1411686380-1953-1-git-send-email-rodrigo.vivi@intel.com
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Daisy Sun <daisy.sun@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

drivers/gpu/drm/i915/i915_drv.h

@@ -945,23 +945,6 @@ struct intel_rps_ei {
 	u32 media_c0;
 };
 
-struct intel_rps_bdw_cal {
-	u32 it_threshold_pct; /* interrupt, in percentage */
-	u32 eval_interval; /* evaluation interval, in us */
-	u32 last_ts;
-	u32 last_c0;
-	bool is_up;
-};
-
-struct intel_rps_bdw_turbo {
-	struct intel_rps_bdw_cal up;
-	struct intel_rps_bdw_cal down;
-	struct timer_list flip_timer;
-	u32 timeout;
-	atomic_t flip_received;
-	struct work_struct work_max_freq;
-};
-
 struct intel_gen6_power_mgmt {
 	/* work and pm_iir are protected by dev_priv->irq_lock */
 	struct work_struct work;
@@ -995,9 +978,6 @@ struct intel_gen6_power_mgmt {
 	bool enabled;
 	struct delayed_work delayed_resume_work;
 
-	bool is_bdw_sw_turbo;	/* Switch of BDW software turbo */
-	struct intel_rps_bdw_turbo sw_turbo; /* Calculate RP interrupt timing */
-
 	/* manual wa residency calculations */
 	struct intel_rps_ei up_ei, down_ei;
 
@@ -2828,8 +2808,6 @@ extern void intel_disable_fbc(struct drm_device *dev);
 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
 extern void intel_init_pch_refclk(struct drm_device *dev);
 extern void gen6_set_rps(struct drm_device *dev, u8 val);
-extern void bdw_software_turbo(struct drm_device *dev);
-extern void gen8_flip_interrupt(struct drm_device *dev);
 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
 				  bool enable);

drivers/gpu/drm/i915/i915_irq.c

@@ -1979,27 +1979,6 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
 				     res1, res2);
 }
 
-void gen8_flip_interrupt(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (!dev_priv->rps.is_bdw_sw_turbo)
-		return;
-
-	if(atomic_read(&dev_priv->rps.sw_turbo.flip_received)) {
-		mod_timer(&dev_priv->rps.sw_turbo.flip_timer,
-				usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies);
-	}
-	else {
-		dev_priv->rps.sw_turbo.flip_timer.expires =
-				usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies;
-		add_timer(&dev_priv->rps.sw_turbo.flip_timer);
-		atomic_set(&dev_priv->rps.sw_turbo.flip_received, true);
-	}
-
-	bdw_software_turbo(dev);
-}
-
 /* The RPS events need forcewake, so we add them to a work queue and mask their
  * IMR bits until the work is done. Other interrupts can be processed without
  * the work queue. */

drivers/gpu/drm/i915/i915_reg.h

@@ -5585,10 +5585,6 @@ enum punit_power_well {
 #define GEN8_UCGCTL6				0x9430
 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
 
-#define TIMESTAMP_CTR		0x44070
-#define FREQ_1_28_US(us)	(((us) * 100) >> 7)
-#define MCHBAR_PCU_C0		(MCHBAR_MIRROR_BASE_SNB + 0x5960)
-
 #define GEN6_GFXPAUSE				0xA000
 #define GEN6_RPNSWREQ				0xA008
 #define   GEN6_TURBO_DISABLE			(1<<31)

drivers/gpu/drm/i915/intel_display.c

@@ -9926,9 +9926,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 	unsigned long flags;
 	int ret;
 
-	//trigger software GT busyness calculation
-	gen8_flip_interrupt(dev);
-
 	/*
 	 * drm_mode_page_flip_ioctl() should already catch this, but double
 	 * check to be safe.  In the future we may enable pageflipping from