Commit 756f1ae8 authored by Paul Mackerras's avatar Paul Mackerras

PPC32: Rework signal code and add a swapcontext system call.

The main thing here is that the signal delivery/return code for real-time
signals has been changed so that the layout of the registers corresponds
with the new ucontext_t definition being used by glibc.  The old ucontext_t
didn't have space to actually store the registers, just a pointer to them,
which made it impossible to implement set/getcontext et al.  The new
ucontext_t includes a mcontext_t which actually contains space to store
all of the general, floating pointer and vector registers.

We now also save the altivec registers on signal delivery and restore them
on return from the signal if the process has ever used altivec (since the
last exec).

Finally this adds a swapcontext system call.  Swapcontext really needs to be
done in the kernel since on PPC, only privileged code can set all three of
CTR, LR and NIA (next instruction address) to arbitrary values.  Also the kernel
know if the process currently owns the FP and altivec units and can optimize
in the case where it doesn't.
parent 016b1894
......@@ -52,6 +52,7 @@ main(void)
DEFINE(THREAD_VR0, offsetof(struct thread_struct, vr[0]));
DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave));
DEFINE(THREAD_VSCR, offsetof(struct thread_struct, vscr));
DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr));
#endif /* CONFIG_ALTIVEC */
/* Interrupt register frame */
DEFINE(STACK_FRAME_OVERHEAD, STACK_FRAME_OVERHEAD);
......@@ -101,7 +102,7 @@ main(void)
DEFINE(_XER, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, xer));
DEFINE(_DAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
DEFINE(_DSISR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
/* The PowerPC 400-class processors have neither the DAR nor the DSISR
/* The PowerPC 400-class & Book-E processors have neither the DAR nor the DSISR
* SPRs. Hence, we overload them to hold the similar DEAR and ESR SPRs
* for such processors. For critical interrupts we use them to
* hold SRR0 and SRR1.
......
......@@ -915,7 +915,9 @@ load_up_altivec:
/* enable use of AltiVec after return */
oris r9,r9,MSR_VEC@h
mfspr r5,SPRG3 /* current task's THREAD (phys) */
li r4,1
li r10,THREAD_VSCR
stw r4,THREAD_USED_VR(r5)
lvx vr0,r10,r5
mtvscr vr0
REST_32VR(0,r10,r5)
......
......@@ -1379,7 +1379,7 @@ _GLOBAL(sys_call_table)
.long sys_clock_gettime
.long sys_clock_getres
.long sys_clock_nanosleep
.long sys_ni_syscall /* reserved for swapcontext */
.long sys_swapcontext
.long sys_tgkill /* 250 */
.long sys_utimes
.long sys_statfs64
......
......@@ -415,6 +415,7 @@ void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp)
memset(current->thread.vr, 0, sizeof(current->thread.vr));
memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));
current->thread.vrsave = 0;
current->thread.used_vr = 0;
#endif /* CONFIG_ALTIVEC */
}
......
This diff is collapsed.
......@@ -848,6 +848,7 @@ struct thread_struct {
/* AltiVec status */
vector128 vscr __attribute((aligned(16)));
unsigned long vrsave;
int used_vr; /* set if process has used altivec */
#endif /* CONFIG_ALTIVEC */
};
......
#ifndef _ASMPPC_UCONTEXT_H
#define _ASMPPC_UCONTEXT_H
/* Copied from i386. */
#include <asm/elf.h>
#include <asm/signal.h>
struct mcontext {
elf_gregset_t mc_gregs;
elf_fpregset_t mc_fregs;
unsigned long mc_pad[2];
elf_vrregset_t mc_vregs __attribute__((__aligned__(16)));
};
struct ucontext {
unsigned long uc_flags;
struct ucontext *uc_link;
stack_t uc_stack;
struct sigcontext uc_mcontext;
sigset_t uc_sigmask; /* mask last for extensibility */
unsigned long uc_flags;
struct ucontext *uc_link;
stack_t uc_stack;
int uc_pad[7];
struct mcontext *uc_regs; /* backward compat */
sigset_t uc_oldsigmask; /* backward compat */
int uc_pad2;
sigset_t uc_sigmask;
/* glibc has 1024-bit signal masks, ours are 64-bit */
int uc_maskext[30];
struct mcontext uc_mcontext;
};
#endif /* !_ASMPPC_UCONTEXT_H */
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